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De Francesco" To: linux-cxl@vger.kernel.org Cc: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, "Fabio M. De Francesco" Subject: Date: Tue, 28 Apr 2026 20:24:33 +0200 Message-ID: <20260428182454.464655-1-fabio.m.de.francesco@linux.intel.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [PATCH 0/2] PCI/CXL: Recover CXL Downstream Ports from PM Init failure CXL r4.0 sec 8.1.5.1 Implementation Note describes a scenario in which a Secondary Bus Reset, a Link Down, or Downstream Port Containment on a CXL Downstream Port prevents Port PM Init from completing when ACS Source Validation is enabled on the Downstream Port. The spec states that another SBR alone does not recover the port and describes a software recovery sequence. Patch 1 extends cxl_reset_bus_function(), the helper backing the cxl_bus PCI/CXL reset method exposed to userspace via sysfs. It saves, clears, and restores ACS Source Validation and Bus Master Enable on the CXL Downstream Port around the SBR it issues. This keeps the userspace cxl_bus reset path from leaving the port unable to complete PM Init. Patch 2 adds a recovery pass during CXL enumeration. For each CXL Downstream Port in a memdev's ancestry, the CXL core checks whether PM Init has completed. If it has not, regardless of what caused the failure, it invokes cxl_reset_bus_function() on the child below the port in the hope of restoring the port to a usable state. CXL enumeration re-runs after events that tear down and re-probe the memdev, including DPC, AER, and Link Down, so those paths reach this recovery. This small series is developed from an old RFC v3: https://lore.kernel.org/linux-cxl/20260330193347.25072-1-fabio.m.de.francesco@linux.intel.com/ Fabio M. De Francesco (2): PCI/CXL: Allow PM Init to complete on cxl_bus reset if ACS SV enabled cxl/core: Recover from PM Init failure via cxl_reset_bus_function() drivers/cxl/core/pci.c | 30 ++++++++++++++++++++ drivers/cxl/core/port.c | 22 +++++++++++++++ drivers/cxl/cxlpci.h | 3 ++ drivers/pci/pci.c | 52 ++++++++++++++++++++++++++++++++++- include/linux/pci.h | 1 + include/uapi/linux/pci_regs.h | 2 ++ 6 files changed, 109 insertions(+), 1 deletion(-) -- 2.53.0