From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA0FF2CCB9 for ; Tue, 28 Apr 2026 22:02:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777413726; cv=none; b=NRnTFBBjW8Zm0antCj/nsJxkaPoZ6thnjmubwmUcF2CnYUzCCmpuVMB9dI3VcydSEOGuUxHaeCsPSC5AGVcd7INPFBl8axQq+loGCDCiC1zbu6wWs7M1GCwbxX8XhGuLJqIffSYC3JYfvBgdeN9FyNfWI+kUQOEQxvtxX3QpGQo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777413726; c=relaxed/simple; bh=r8vkVzBEwB9e4ptIQnnS1XAbCkLC1zWFo2SH/aid8HY=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=dmzm5yJCB/GWywlXAYJ7hVWm8qAhTPAKOg86VxP1XUgDXzoLahHBEemVaVfbDm5kDVoaC3dHkf4I2qNa+IuPTmF10ZNtvwjHm9tjNpjVmylAvjb1b5gZTAGtRSzXV7KnEPHkgevbIX1fz1aimx7/nHefJQBtjMCJ8KxRBVOh/wo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s60LYOcC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s60LYOcC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4F8E1C2BCAF; Tue, 28 Apr 2026 22:02:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777413726; bh=r8vkVzBEwB9e4ptIQnnS1XAbCkLC1zWFo2SH/aid8HY=; h=From:To:Cc:Subject:Date:From; b=s60LYOcCIC09oAq47ZB03t98DB5+3zL5YU6azw8luqgRo2vF9n2ukvxyaRbhYZtl/ 37EZkpl2vTMe31fZ1xW2NcKSmRI6R5f5ZXPNg/cp87gVy1/W4/OY3VofxsRsnKjqcF ZYBq6z8O1+bWWd+HOlXw4+ySiCCPSjuAJaEPRSjho1lIbErzfm0aRF61FWJzfTw6id aHlDaJQ32EK1WIDK2Kt1mQyhGYjHE4dCHka8wv99fHCIaWiwfREmASNhl8pA/rUVhN fgBOROnSuvCAyJX06wDgUKfqsvHckxDndQcNBAFP6pAAxjdbCEb432vzYVl8bPvVk9 QKgA5+qdl92pA== From: "Rob Herring (Arm)" To: Russell King Cc: Arnd Bergmann , Vishnu Banavath , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM: Kconfig: Disable ARM_VIRT extension if XIP_KERNEL Date: Tue, 28 Apr 2026 16:58:15 -0500 Message-ID: <20260428215815.2884392-2-robh@kernel.org> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Vishnu Banavath XIP is intended to execute kernel inplace and typically from flash and is used mostly on low memory devices. .macro store_primary_cpu_mode reg1, reg2, reg3 mrs \reg1, cpsr and \reg1, \reg1, #MODE_MASK adr \reg2, .L__boot_cpu_mode_offset ldr \reg3, [\reg2] str \reg1, [\reg2, \reg3] As text section is in flash memory and data section is in RAM. L__boot_cpu_mode_offset would evaluate to address based on virtual addresses provided by linker script. At this stage the MMU is OFF. The logic used based stored @L__boot_cpu_mode_offset on the offset between the boot_cpu_mode in data section and the location of L__boot_cpu_mode_offset can't be used along with PC to fetch the value of boot_cpu_mode doesn't work. Signed-off-by: Vishnu Banavath Signed-off-by: Rob Herring (Arm) --- This patch is from Alif E8 SoC tree which I'm working on. It's originally from corstone700 trees. arch/arm/mm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 7b27ee9482b3..e2f5d3d7d3fb 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -705,6 +705,7 @@ config ARM_THUMBEE config ARM_VIRT_EXT bool + depends on MMU && !XIP_KERNEL default y if CPU_V7 help Enable the kernel to make use of the ARM Virtualization -- 2.53.0