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Thu, 30 Apr 2026 02:52:21 -0700 From: Ashish Mhetre To: , , CC: , , , Ashish Mhetre Subject: [PATCH V3 3/3] memory: tegra: Restore MC interrupt masks on resume Date: Thu, 30 Apr 2026 09:52:02 +0000 Message-ID: <20260430095202.1167651-4-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260430095202.1167651-1-amhetre@nvidia.com> References: <20260430095202.1167651-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|DS4PR12MB9633:EE_ X-MS-Office365-Filtering-Correlation-Id: e648401a-e776-40e6-5a69-08dea69e3708 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|22082099003|18002099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: kHjF+cKDC2qhjTuK3lGqvnrqfqZUfRDWMeCZLvPbxTrLvPRvbRWMTWoo1QXq5DVBLhx7tgpXwgGVjQ+sP/7TDCqXqBVWMWcPXYiV1nYE/1aJPrPQQEIz77V2jLYmBy97Yi3+TZYIEOE8RfBz9LE02al7zgy8mF6LUB3o+pudTEdr4O6QVWEg0vpFscp3sw+4qy0j2l59dd91BIljEHMvFBS/IXDWkDVfmJxGnHgtUWNb+MwHxjlqa9XI2+JQuw1Tha/OmlGlKMu46iync2DWq3K7qjlUbZTkU4QjNpq6nS5Q3mUVuCpQ+DStntMKpHW3TNkrF1KwPRnO7skeKOmZBjXKxVZ+H9GOm+qZdX0iRY/9AB4T4u103OIXyflR8ESdSn2TtJlCMxBQGQ0YJvJpiS7zmuqtdawbSfrnKflJpZTnn6Yh4EyWIJzpYe2VAUCD X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2026 09:52:38.9980 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e648401a-e776-40e6-5a69-08dea69e3708 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9633 The MC interrupt mask registers lose their state across SC7. Without re-applying them on resume, MC interrupts that were enabled at probe remain masked after wake, so any post-resume MC error goes unreported. Factor the existing intmask programming out of tegra_mc_probe() into tegra_mc_setup_intmask() and reuse it from the system resume callback so the mask state is restored on wake. Signed-off-by: Ashish Mhetre --- drivers/memory/tegra/mc.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 64e41338cdf2..cfcfc7291106 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -911,6 +911,19 @@ static void tegra_mc_num_channel_enabled(struct tegra_mc *mc) } } +static void tegra_mc_setup_intmask(struct tegra_mc *mc) +{ + unsigned int i; + + for (i = 0; i < mc->soc->num_intmasks; i++) { + if (mc->soc->num_channels) + mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask, + mc->soc->intmasks[i].reg); + else + mc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg); + } +} + static int tegra_mc_probe(struct platform_device *pdev) { struct tegra_mc *mc; @@ -971,13 +984,7 @@ static int tegra_mc_probe(struct platform_device *pdev) } } - for (i = 0; i < mc->soc->num_intmasks; i++) { - if (mc->soc->num_channels) - mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask, - mc->soc->intmasks[i].reg); - else - mc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg); - } + tegra_mc_setup_intmask(mc); } if (mc->soc->reset_ops) { @@ -1018,6 +1025,8 @@ static int tegra_mc_resume(struct device *dev) if (mc->soc->ops && mc->soc->ops->resume) mc->soc->ops->resume(mc); + tegra_mc_setup_intmask(mc); + return 0; } -- 2.50.1