From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BC4D2C21F2 for ; Sat, 2 May 2026 21:26:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777757172; cv=none; b=tKaYMaL43yjUEiuj41F2d8cqfql0pt7IXPns5joiuwme1khOldFDjK3qTqo7NJ2Zuulnzi4+2HfWrblOwRWLcEeIlYAGgb5lAip0d7RsRF4jjKAAql/UgkkMFngVZRuQyVDwJyhBctY1zSfF/duRjROmT4YdetywEycEvGv6eQY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777757172; c=relaxed/simple; bh=qde0OXr1DfeRkdHYJGgcNHTGCqg7+u0WqH5JxrUNo6c=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C8nCd5vGAe4idxLB8a0GqC4KFQdaCPPT3M7kqGCb7eUphOkY2qp+ykzz/axWDxrIeFgdl5wutTrpJ6ym7aiocigak3mYuZHwr84ZJmPseCcn48sAxDOcKTbrRzk1Y/2QDY8sOvH+ltcUVPB7QHDmCIQXBEwcmBj03ufqAqhIM0s= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=BChPijZQ; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BChPijZQ" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-488d2079582so31499045e9.2 for ; Sat, 02 May 2026 14:26:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777757169; x=1778361969; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:subject:cc:to:from:date:from:to:cc:subject:date :message-id:reply-to; bh=MBy/HeTLltFwJiiHUn7fQmIc+nh2Kj1V0A53WwiwSzE=; b=BChPijZQBXvJUIebrD41KN5sPBQwVqhZGjXzL8oGtiYppQMOGyk9sMmSTg5KS2EOM1 LEGxKCDKSgsbjmLDXrtjNdYTJknSSxL05Si4amrBqoUv7348evL+CjTiol1oITM7uD/F qlG1O023r6+N6KcBx5UHeJ+Fpp7Q60OFXtn9Qt1nnGKDxGqD8U//fNrWoPJZphsmtlkG qKkmdUmIe6NFLJbjRiBXNPucf1/thichQeuUBtBy3DqbFPKLlCv+JKmwp0R0/LmWJFpP zRah68rXkUlH9vY+bW2bBBqSunQUSTRYc3wB8uGgiDu0DZzzDZYx9fjkGHwImbapVc+x Fyow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777757169; x=1778361969; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:subject:cc:to:from:date:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=MBy/HeTLltFwJiiHUn7fQmIc+nh2Kj1V0A53WwiwSzE=; b=M1OAf0Zl41NsQtKVFmODiAnThMux3sHufJxp4QmlkPga+aSnu7acFsAR3qW6Ems3V5 RPHdlQTCf7xvknDgcsbOvfVk4/JIkg3cDqHGGkVs4IcU7FgzVPgkgvVa8N9NFLhb6kzi qGTFQOnTWTYkc/Jx46IMJnSk5ahpZWc2pAMHFZM3AmqBNG+0d8re/Xav46hu9T1lMoj8 nUGCtrG/jdZXYBabn+A2xMhGMvnSWfa62wycBMqr3gVWneqlQmg8hqUpJuigW4gqFi6b kTss6RCL28N7pVHZZrZlw0Y2nnhx5UhwErgiGneH8y/LhuAaU8jaFGwMlhlp7P3pdqdo kOPA== X-Forwarded-Encrypted: i=1; AFNElJ8QQFNA7z2nuGank2II0IH58xoc3SnPhD0xMawz4d01+f27DKeuYyuhb7dXjjucVNBRnjrHm6BbWWhXEyc=@vger.kernel.org X-Gm-Message-State: AOJu0YzrjSxM0JJf6kHj/jow2mre1ma0/9p1UNaOkXdBqqTPMkKjyB/G kXUs+sBcZopY2kzNbwn4MzGo6lYt6xppJb1VWik94FZV8G5iKyju7LzeEPJxaHPp X-Gm-Gg: AeBDieuBCl4UhNTNWB1NabsbLmC5PBok9XG9nSMj+7dWGNjABzRZET1f2+/4Q+jT+7Z PtX9Y4b27xMF+9/lOw9Rq/X6U6bxzqozaj+fIcwS24xlAQQDdycdJsd8sOBoDYK+Vr1ODl5GQJz b42ZIA9CykKbZzT2th7+oI3+FgzXeXKJO+mxdMyS0F2nuhV6TslczBazxbod8stdeTQbVzOQ8SB y3llloWEz6CAf5d6jCl1q7h88fFfgFDXEZx4PAosmrYftdkRL76s0MlmA6gn1r6B9bjyjNxyZhp Eb2PRgIAiXthULnOZc/5fiBVby3fOBJWzxEfC9un+5zlN+85vqC03im1rt0uEBwmQbAhGuvLm5C BKWnqh6pwbgFeEnmYKNPKkKcCkvmlRCde+S801c11DkE9qLJ9wiKQydEF0EhhoD4NpmC1CpT4wG E/go8l0yZYlcwZ4ARDE3We/DxNGfSDccjUcEuWruW/KbAoKY8vl8eTBO38LX3XxrkADY4PAX/wU ow= X-Received: by 2002:a05:600c:3b8c:b0:489:284:44ab with SMTP id 5b1f17b1804b1-48a9864461bmr74732855e9.12.1777757169012; Sat, 02 May 2026 14:26:09 -0700 (PDT) Received: from pumpkin (82-69-66-36.dsl.in-addr.zen.co.uk. [82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a82307f28sm357501235e9.13.2026.05.02.14.26.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 May 2026 14:26:08 -0700 (PDT) Date: Sat, 2 May 2026 22:26:07 +0100 From: David Laight To: Willy Tarreau Cc: Daniel Palmer , linux@weissschuh.net, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 1/2] tools/nolibc: fcntl: Add fallocate() Message-ID: <20260502222607.4ab68291@pumpkin> In-Reply-To: References: <20260430164125.1106350-1-daniel@thingy.jp> <20260430164125.1106350-2-daniel@thingy.jp> <20260501091831.7abc39f1@pumpkin> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Sat, 2 May 2026 05:00:06 +0200 Willy Tarreau wrote: > On Fri, May 01, 2026 at 09:18:31AM +0100, David Laight wrote: > > On Fri, 1 May 2026 01:41:24 +0900 > > Daniel Palmer wrote: > > > > > Add fallocate(). > > > > > > Some special care is needed to put the offset and size > > > into the syscall parameters for 32bit machines, x32, > > > and mipsn32. > > > > > > For x32 we can just check if the kernel long size is the > > > same as off_t and use the same path as x86_64. > > > > > > For mipsn32 we override the generic version and provide > > > one that does the right thing. > > > > > > Signed-off-by: Daniel Palmer > > > --- > > > tools/include/nolibc/arch-mips.h | 11 +++++++++++ > > > tools/include/nolibc/fcntl.h | 33 ++++++++++++++++++++++++++++++++ > > > tools/include/nolibc/sys.h | 8 ++++++++ > > > 3 files changed, 52 insertions(+) > > > > > > diff --git a/tools/include/nolibc/arch-mips.h b/tools/include/nolibc/arch-mips.h > > > index 1400653c76c1..e4e42f2bcaf4 100644 > > > --- a/tools/include/nolibc/arch-mips.h > > > +++ b/tools/include/nolibc/arch-mips.h > > > @@ -6,6 +6,7 @@ > > > > > > #ifndef _NOLIBC_ARCH_MIPS_H > > > #define _NOLIBC_ARCH_MIPS_H > > > +#include > > > > > > #include "compiler.h" > > > #include "crt.h" > > > @@ -256,6 +257,16 @@ > > > _arg4 ? -_num : _num; \ > > > }) > > > > > > +/* The generic version of this will split offset and size for _ABIN32, > > > + * override it and do the right thing here. > > > + */ > > > +static __attribute__((unused)) > > > +int _sys_fallocate(int fd, int mode, off_t offset, off_t size) > > > +{ > > > + return __nolibc_syscall4(__NR_fallocate, fd, mode, offset, size); > > > +} > > > +#define _sys_fallocate _sys_fallocate > > > + > > > #endif /* _ABIO32 */ > > > > > > #ifndef NOLIBC_NO_RUNTIME > > > diff --git a/tools/include/nolibc/fcntl.h b/tools/include/nolibc/fcntl.h > > > index 014910a8e928..dbc99188a49e 100644 > > > --- a/tools/include/nolibc/fcntl.h > > > +++ b/tools/include/nolibc/fcntl.h > > > @@ -14,6 +14,9 @@ > > > #include "types.h" > > > #include "sys.h" > > > > > > +/* For fallocate() modes */ > > > +#include > > > + > > > /* > > > * int openat(int dirfd, const char *path, int flags[, mode_t mode]); > > > */ > > > @@ -80,4 +83,34 @@ int creat(const char *path, mode_t mode) > > > return open(path, O_CREAT | O_WRONLY | O_TRUNC, mode); > > > } > > > > > > +/* > > > + * int fallocate(int fd, int mode, off_t offset, off_t size); > > > + */ > > > + > > > +#if !defined(_sys_fallocate) > > > +static __attribute__((unused)) > > > +int _sys_fallocate(int fd, int mode, off_t offset, off_t size) > > > +{ > > > + /* > > > + * For 32 bit machines __kernel_long_t will be 4, off_t will be 8 > > > + * and we need to split offset and size, for 64 machines we can use > > > + * the values as-is. > > > + */ > > > + const bool offsetsz_two_args = sizeof(__kernel_long_t) != sizeof(off_t); > > > > I don't think you care about the size of off_t. > > Were it to be 4 the code would be badly wrong. > > > > > + > > > + if (offsetsz_two_args) > > > + return __nolibc_syscall6(__NR_fallocate, fd, mode, > > > + __NOLIBC_LLARGPART(offset, 0), __NOLIBC_LLARGPART(offset, 1), > > > + __NOLIBC_LLARGPART(size, 0), __NOLIBC_LLARGPART(size, 1)); > > > + else > > > + return __nolibc_syscall4(__NR_fallocate, fd, mode, offset, size); > > > +} > > > > The above might be more readable as: > > if (sizeof(__kernel_long_t) == 8) > > /* 64 bit, values fit in single arguments */ > > return __nolibc_syscall4(__NR_fallocate, fd, mode, offset, size); > > > > /* 32 bit, values need splitting, order depends on endianness */ > > /* This test for endianness doesn't rely on any pre-processor defines */ > > if (({union {int x; char c;} u; u.x = 1; u.c;})) > > /* Little endian */ > > return __nolibc_syscall6(__NR_fallocate, fd, mode, > > offset, offset >> 32, size, size >> 32); > > /* Big endian */ > > return __nolibc_syscall6(__NR_fallocate, fd, mode, > > offset >> 32, offset, size >> 32, size); > > Honestly David, I find Daniel's version way more readable :-) Precisely > because the repeated variations are abstracted with this more readable > macro. If it was used only once I could possibly agree. Even the > endianness test is hard to read, better rely on __BYTE_ORDER__ for > this. I did say 'might' :-) and I should probably have used __BYTE_ORDER__. Looking again, the code is trying to copy what the compiler generates when it passes a 64bit quantity on stack or in 2 registers. So f(a, b, c, d) is traditionally 'push d; push c; push b, push a; call f'. With the normal 'stack grows down' this gives (in increasing addresses): return address a b c d If 'b,c' is replaced by a 64bit value then you want the stack memory to contain the correct representation of a 64bit value. So for LE you need to pass the low part before the high part. But there is one architecture (parisc) where the stack goes the other way. It is BE (I believe), but would need the LE argument order. I think all the conditionals could be moved out of the fallocate code. I'm not sure of the exact pre-processor conditionals but something like: #if (__BITS_PER_LONG == 64) || defined(x86_x32) || defined(mips_n32) #define __NOLIBC_ARG64(x) (x) #else /* The on-stack data has to be in the natural order for a 64bit value. */ #if (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN_) ^ defined(STACK_GROWS_UP) #define __NOLIBC_ARG64(x) ((int)(x)), ((int)((long long)(x) >> 32)) #else #define __NOLIBC_ARG64(x) ((int)((long long)(x) >> 32)), ((int)(x)) #endif #endif Then (if I've got it right): static __attribute__((unused)) int _sys_fallocate(int fd, int mode, off_t offset, off_t size) { return _syscall(__NR_fallocate, fd, mode, __NOLIBC_ARG64(offset), __NOLIBC_ARG64(size)); } There is the other problem that arm32 (and maybe others) requires the 64bit variable be aligned in the stack frame. So f(int a, long long b) is effectively f(int a, int pad, long long b). (This usually causes grief with lseek().) So a pad might be needed for some system calls on some 32bit architectures. This could be done with something that expands to '' or '0,'. David > > Cheers, > Willy