From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CE813BE623 for ; Mon, 4 May 2026 11:34:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777894454; cv=none; b=qELpR8OaBU3Yzs3uRR72YlvxqemYa50RkA97ksDvlhmcP/Atfk7Du6iY+HJ48FswiwEfqO+lHszFLPWH1vGeBLVW/MRAg5fcyOdwSv9Oi5gnRyfS5VOrikIcXQw+dvHJj/7QQNs/fN5J0HVWZUyBr6Qn8alQH5jxyOwwrstiGLU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777894454; c=relaxed/simple; bh=rOnIi5Au/er0JAR2gXsjbHXOLsZxgafGwGrpu94iBhA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DtBKKsEbkQ1qpSVRKB8tYNWLibQHbuVmDLlU4l7cE46+uZ7kq82Rw8svl6jPLhjo/6h+l130dR+cp9kQ7v2ua4pilM6crFcScQ3ZHv16QhQ7YIEFOPa5mh52vhl/+X9q7SV3L05I7SZ8KYISdi10EvsNAeMQlFl3e5CumLFng5A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jzLk1PLS; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jzLk1PLS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777894451; x=1809430451; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rOnIi5Au/er0JAR2gXsjbHXOLsZxgafGwGrpu94iBhA=; b=jzLk1PLSOIMdfTuSCjHMbFdV8zP3aRlSdBrBTFpogadduFQVbXpY3BWd 8VVCJHDT7Ki0SbFPUHPIaA3gQ5vVRLlapXi5LEw7k72p1sH9RLvJ4ahID jlh2kGcST50gtDdMWwqBnWeZpMcLKg+lxi7/RRROS6dsXkdXtvAIYvsu6 VPM2+wH0uKYgt2PCafvAhJcbxOLlLi7SG1y/AJURjIdw3pghG+Cane6YU v5sSa3Qa9CSKmK6pA24VICfAKgo/PRW+Y+/oC1T0oVEin+nsIqRuhOCMp dIwkMH/1VH/tq4+ZMLtBt5EUURlh0LS3nXAyjdfmr5N9qe6GEWftbiq/u g==; X-CSE-ConnectionGUID: zNt/Lmv9QWypV80gK5noRw== X-CSE-MsgGUID: SagiPQhgQr+LA17/Z9Ji8Q== X-IronPort-AV: E=McAfee;i="6800,10657,11775"; a="81315153" X-IronPort-AV: E=Sophos;i="6.23,215,1770624000"; d="scan'208";a="81315153" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2026 04:34:10 -0700 X-CSE-ConnectionGUID: hkqgU0VLSiGFTF+qCKBpGg== X-CSE-MsgGUID: ty15N4aNQCKe3IojAWGpWg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,215,1770624000"; d="scan'208";a="240478211" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.92]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2026 04:34:09 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 04/16] i3c: mipi-i3c-hci: Wait for DMA ring restart to complete Date: Mon, 4 May 2026 14:33:40 +0300 Message-ID: <20260504113352.38490-5-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260504113352.38490-1-adrian.hunter@intel.com> References: <20260504113352.38490-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: 8bit Although hci_dma_dequeue_xfer() is serialized against itself via control_mutex, this does not guarantee that a DMA ring restart triggered by a previous invocation has fully completed. When the function is called again in rapid succession, the DMA ring may still be transitioning back to the running state, which may confound or disrupt further state changes. Address this by waiting for the DMA ring restart to complete before continuing. Signed-off-by: Adrian Hunter --- Changes in V2 and V3: None drivers/i3c/master/mipi-i3c-hci/dma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mipi-i3c-hci/dma.c index 314635e6e190..28614fdbf558 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -617,6 +617,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } /* restart the ring */ + reinit_completion(&rh->op_done); mipi_i3c_hci_resume(hci); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP); @@ -625,6 +626,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, spin_unlock_irq(&hci->lock); + wait_for_completion_timeout(&rh->op_done, HZ); + return did_unqueue; } -- 2.51.0