From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88D6D2D837C for ; Mon, 4 May 2026 11:02:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777892544; cv=none; b=KF7vbiHOD0V3EUQRQG9+jad1Yj6Z38p0KdFoOHy0YPZLdZOgRt/yVs6Aon/9HwMh2BhcYKSpSxoJIqzuJk71MLzrYucIn0fWM49FQFwJE4K+wTmazb6aTJWOzapU8ylF/G0s4+qPfau2RQR8SOE+ceJaXctpEhG1Kw0iFDiSEPs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777892544; c=relaxed/simple; bh=YIIRoU83Rvr3BCz4suh5d1PWHieSo4Fl6v6kR4sQ0xY=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lTUAgkdLBNodGjGUQfgKN0+n9WISMQ8sZYTdHxvvYtJQbzEzgLp3E60PhAmy1p1P7di7ohDP1AK1K2bLlmX/SDDKD9EI1rj9sx17WPY8PafvveTHdiVoTS0XZCpl7ADGIQlbXUZlSKqSTZMhRv37MSuE8H7WT4TFeUMhe+1+glo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=d0k7a8+N; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="d0k7a8+N" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1777892540; bh=YIIRoU83Rvr3BCz4suh5d1PWHieSo4Fl6v6kR4sQ0xY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=d0k7a8+NIU0ryK+11CcaVuBa37YTL3cIu2yOxFfg6a3c/mkvUhUabWhh2YMtA4CfJ Rgd4SwQeLlsh8FbuKZoV1HhaPv9lIo+hz5LWtnWSubjQ1iPOV0l4wCEvD+c2VoAfl+ JkRk6Wjc8CsQ/EDE0gTJwXYa6/XHBOYaobaP5OibB84E0vFffwfYdP1knodfhN7FUo AmLNsTAL9On7DsyOCHPQxbTr6IvEOAn5xkmc9NUmu3G2Pi0pRsaSVonw/rtER9UVkl 0Vr7SHWcxcK7tGbdzl9VP6jwTFsSWH5NgSfDiXBSiD/eVAxOmWjwwBGsSBrng36YPw 9sB5TKbMNPhVA== Received: from fedora (unknown [100.64.0.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbrezillon) by bali.collaboradmins.com (Postfix) with ESMTPSA id 5477017E124B; Mon, 4 May 2026 13:02:20 +0200 (CEST) Date: Mon, 4 May 2026 13:02:15 +0200 From: Boris Brezillon To: Steven Price Cc: Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 08/10] drm/panthor: Automatically enable interrupts in panthor_fw_wait_acks() Message-ID: <20260504130215.0222b3bd@fedora> In-Reply-To: <446e9d1f-b6be-42fa-bd2b-f4fcbc130f70@arm.com> References: <20260429-panthor-signal-from-irq-v1-0-4b92ae4142d2@collabora.com> <20260429-panthor-signal-from-irq-v1-8-4b92ae4142d2@collabora.com> <446e9d1f-b6be-42fa-bd2b-f4fcbc130f70@arm.com> Organization: Collabora X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Fri, 1 May 2026 15:20:17 +0100 Steven Price wrote: > On 29/04/2026 10:38, Boris Brezillon wrote: > > Rather than assuming an interrupt is always expected for request > > acks, temporarily enable the relevant interrupts when the polling-wait > > failed. This should hopefully reduce the number of interrupts the CPU > > has to process. > > > > Signed-off-by: Boris Brezillon > > It seems to work, although I'm lightly uneasy about this because I'm not > entirely sure whether the FW will immediately see the updates to > ack_irq_mask and therefore whether there's a possibility to miss an > event and be stuck waiting for the timeout. > > Memory models are not my strong point, OpenAI tells me the sequence > should be something like: > > scoped_guard(spinlock_irqsave, lock) { > u32 ack_irq_mask = READ_ONCE(*ack_irq_mask_ptr); > > WRITE_ONCE(*ack_irq_mask_ptr, ack_irq_mask | req_mask); > } Is this really needed? In which situation would the compiler/CPU decide to re-order this read_update_modify sequence? > > /* > * The FW interface can be mapped write-combine/Normal-NC. I'm not too sure I see what the non-cached property has to do with it. If it was cached we would still need this memory barrier, and in addition, we'd need a cache flush if the FW is not IO-coherent. >Make sure the > * IRQ mask update is visible to the FW before sleeping waiting for > the IRQ. > */ > wmb(); > > Which seems plausible. But I've long ago learnt that plausible doesn't > mean much when dealing with memory models! Yeah, I'm not too sure. I was honestly expecting the spinlock guard to act as a memory barrier already, but maybe it's not enough.