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Miller" , Donald Hunter , Eric Dumazet , Jakub Kicinski , Jonathan Corbet , Leon Romanovsky , Mark Bloch , Michal Schmidt , Paolo Abeni , Pasi Vaananen , Petr Oros , Prathosh Satish , Saeed Mahameed , Shuah Khan , Simon Horman , Tariq Toukan , Vadim Fedorenko , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org Subject: [PATCH net-next v3 1/2] dpll: add fractional frequency offset to pin-parent-device Date: Mon, 4 May 2026 17:53:39 +0200 Message-ID: <20260504155340.411063-2-ivecera@redhat.com> In-Reply-To: <20260504155340.411063-1-ivecera@redhat.com> References: <20260504155340.411063-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Add both fractional-frequency-offset (PPM) and fractional-frequency-offset-ppt (PPT) attributes to the pin-parent-device nested attribute set, alongside the existing top-level pin attributes. Both carry the same measurement at different precisions. Distinguish the two contexts in the ffo_get callback by passing dpll=NULL for the top-level call and a valid dpll pointer for the nested per-parent call. This allows drivers to report a different value per parent DPLL if needed. Update mlx5 and zl3073x drivers to return -ENODATA for the context they do not yet support. Add documentation for both FFO attributes to dpll.rst. Signed-off-by: Ivan Vecera --- Documentation/driver-api/dpll.rst | 15 ++++++++++ Documentation/netlink/specs/dpll.yaml | 28 ++++++++++++------- drivers/dpll/dpll_netlink.c | 23 +++++++-------- drivers/dpll/dpll_nl.c | 2 ++ drivers/dpll/zl3073x/dpll.c | 4 +++ .../net/ethernet/mellanox/mlx5/core/dpll.c | 4 +++ 6 files changed, 55 insertions(+), 21 deletions(-) diff --git a/Documentation/driver-api/dpll.rst b/Documentation/driver-api/dpll.rst index 37eaef785e304..c21aea6b52f6b 100644 --- a/Documentation/driver-api/dpll.rst +++ b/Documentation/driver-api/dpll.rst @@ -258,6 +258,21 @@ in the ``DPLL_A_PIN_PHASE_OFFSET`` attribute. ``DPLL_A_PHASE_OFFSET_MONITOR`` attr state of a feature =============================== ======================== +Fractional frequency offset +=========================== + +The fractional frequency offset (FFO) is reported through two attributes +that carry the same measurement at different precisions: + +- ``DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET`` in PPM (parts per million) +- ``DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT`` in PPT (parts per trillion) + +Both attributes appear at the top level of a pin and inside each +``pin-parent-device`` nest. The driver's ``ffo_get`` callback receives +a NULL ``dpll`` pointer for the top-level context and a valid pointer +for the per-parent context, allowing it to distinguish the two if +needed (e.g. report a different measurement per parent DPLL). + Frequency monitor ================= diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml index c45de70a47ce6..91a172617b3a9 100644 --- a/Documentation/netlink/specs/dpll.yaml +++ b/Documentation/netlink/specs/dpll.yaml @@ -448,12 +448,14 @@ attribute-sets: name: fractional-frequency-offset type: sint doc: | - The FFO (Fractional Frequency Offset) between the RX and TX - symbol rate on the media associated with the pin: - (rx_frequency-tx_frequency)/rx_frequency + The FFO (Fractional Frequency Offset) of the pin. + At top level this represents the RX vs TX symbol rate + offset on the media associated with the pin. Inside + the pin-parent-device nest it represents the frequency + offset between the pin and its parent DPLL device. Value is in PPM (parts per million). - This may be implemented for example for pin of type - PIN_TYPE_SYNCE_ETH_PORT. + This is a lower-precision version of + fractional-frequency-offset-ppt. - name: esync-frequency type: u64 @@ -492,12 +494,14 @@ attribute-sets: name: fractional-frequency-offset-ppt type: sint doc: | - The FFO (Fractional Frequency Offset) of the pin with respect to - the nominal frequency. - Value = (frequency_measured - frequency_nominal) / frequency_nominal + The FFO (Fractional Frequency Offset) of the pin. + At top level this represents the RX vs TX symbol rate + offset on the media associated with the pin. Inside + the pin-parent-device nest it represents the frequency + offset between the pin and its parent DPLL device. Value is in PPT (parts per trillion, 10^-12). - Note: This attribute provides higher resolution than the standard - fractional-frequency-offset (which is in PPM). + This is a higher-precision version of + fractional-frequency-offset. - name: measured-frequency type: u64 @@ -534,6 +538,10 @@ attribute-sets: name: operstate - name: phase-offset + - + name: fractional-frequency-offset + - + name: fractional-frequency-offset-ppt - name: pin-parent-pin subset-of: pin diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c index 05cf946b4be5e..e1158033ba0a1 100644 --- a/drivers/dpll/dpll_netlink.c +++ b/drivers/dpll/dpll_netlink.c @@ -417,30 +417,27 @@ dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin, static int dpll_msg_add_ffo(struct sk_buff *msg, struct dpll_pin *pin, struct dpll_pin_ref *ref, + const struct dpll_device *dpll, void *dpll_priv, struct netlink_ext_ack *extack) { const struct dpll_pin_ops *ops = dpll_pin_ops(ref); - struct dpll_device *dpll = ref->dpll; s64 ffo; int ret; if (!ops->ffo_get) return 0; - ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(dpll, pin), - dpll, dpll_priv(dpll), &ffo, extack); + ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(ref->dpll, pin), + dpll, dpll_priv, &ffo, extack); if (ret) { if (ret == -ENODATA) return 0; return ret; } - /* Put the FFO value in PPM to preserve compatibility with older - * programs. - */ - ret = nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, - div_s64(ffo, 1000000)); - if (ret) + if (nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, + div_s64(ffo, 1000000))) return -EMSGSIZE; - return nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, + return nla_put_sint(msg, + DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, ffo); } @@ -686,6 +683,10 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin, if (ret) goto nest_cancel; ret = dpll_msg_add_phase_offset(msg, pin, ref, extack); + if (ret) + goto nest_cancel; + ret = dpll_msg_add_ffo(msg, pin, ref, ref->dpll, + dpll_priv(ref->dpll), extack); if (ret) goto nest_cancel; nla_nest_end(msg, attr); @@ -748,7 +749,7 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin, ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack); if (ret) return ret; - ret = dpll_msg_add_ffo(msg, pin, ref, extack); + ret = dpll_msg_add_ffo(msg, pin, ref, NULL, NULL, extack); if (ret) return ret; ret = dpll_msg_add_measured_freq(msg, pin, ref, extack); diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c index 58235845fa3d5..b1d9182c7802f 100644 --- a/drivers/dpll/dpll_nl.c +++ b/drivers/dpll/dpll_nl.c @@ -19,6 +19,8 @@ const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_OPERSTATE + [DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3), [DPLL_A_PIN_OPERSTATE] = NLA_POLICY_RANGE(NLA_U32, 1, 4), [DPLL_A_PIN_PHASE_OFFSET] = { .type = NLA_S64, }, + [DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET] = { .type = NLA_SINT, }, + [DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT] = { .type = NLA_SINT, }, }; const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1] = { diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c index 6fd718696de0d..f2d430d1a8e7b 100644 --- a/drivers/dpll/zl3073x/dpll.c +++ b/drivers/dpll/zl3073x/dpll.c @@ -299,6 +299,10 @@ zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv, { struct zl3073x_dpll_pin *pin = pin_priv; + /* Only rx vs tx symbol rate FFO is supported */ + if (dpll) + return -ENODATA; + *ffo = pin->freq_offset; return 0; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c index bce72e8d1bc31..ef2c58c390efa 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c @@ -306,6 +306,10 @@ static int mlx5_dpll_ffo_get(const struct dpll_pin *pin, void *pin_priv, struct mlx5_dpll *mdpll = pin_priv; int err; + /* Only rx vs tx symbol rate FFO is supported */ + if (dpll) + return -ENODATA; + err = mlx5_dpll_synce_status_get(mdpll->mdev, &synce_status); if (err) return err; -- 2.53.0