From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 266CA3F20ED for ; Mon, 4 May 2026 19:08:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777921734; cv=none; b=AETdIZ9OhnRODUkBolxjRtJvvDouyVn+cDGq0jQYPzQhYV6lH20/pBAUSn6e1nNpYJQqmhGoqjUOz5NNS/9GYt/NGReXV551jtkL+ckcmeL8XQ6KQKvLS+wHx6E5/oC9wUEoHxy7syltGZXtac7cAPapCE8RWsqZ7isdZohiwpo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777921734; c=relaxed/simple; bh=3ZK8+sf7TdzMV+59OQ6CIU6fiDFZ7LVgZ0ccGqZAxCE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FFYgvmbusOtrNrx+QY8LGIw0EQsOijXFq1DncV92JnX4qtFRrChNz2EMx1nEqtgDUQI4Udj9uaoC7GiLlZyNbgvtOxjpebjdJ2OeVF0CtpVCHATUK4vkE/rkwuH3QneK/a7E2Wjd6uh4H7wD2gelvCiEDQqBtQ9MQJYoMR0WgrM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=PaFmOxjs; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=FBLxTBpV; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="PaFmOxjs"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="FBLxTBpV" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 644FOtfU1346410 for ; Mon, 4 May 2026 19:08:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=k0Z25Ri0qsZ f4kdu4iu99TPanG49TW6penprmyqGHx0=; b=PaFmOxjsXBrkd/tQKSEVFdcgL1C yyaky2OyHEiB6aT8wjuO0n7hFAKM+MOmWiCuxMQwxiVJ+j12kKKf7amX+0aJQCCb UGcy91PzYaZyP7oeyFEIEsaWVwFUDtW8EK5uokOp0+KnHFdCVwGxu4V8zetA1tXt 5ACrDsRZ6SaTg5C8ID5vZGu/ghIWmeGVOz6NqBC1oGpqu0JQlaPFkij8jQh1D4VD mqy0Oe1haBxSBJmxvADdDSIwNho5eZt26+548JeWKROPgui4AZ1mG44ef/VcoCyo RP2/GJbNt8c8mIErL4wwobLrJYY8mWNmmgRZSyvf/aE+GF/75y0qb44ZZhw== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dxx2x8vk0-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 04 May 2026 19:08:51 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2b79f4b35b7so41207405ad.0 for ; Mon, 04 May 2026 12:08:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1777921730; x=1778526530; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k0Z25Ri0qsZf4kdu4iu99TPanG49TW6penprmyqGHx0=; b=FBLxTBpVBRRwJ+eb7tJ90KJEv0VPj6r6XIYMXzTW8K74VTV80QyB1l7mg+y7zjZfrV Q/JQN3PXpMn5IBOKSB/4/wAY6teauvsdv4ANl2RZmsUfMMxwWWWEUX0xZUZJkvmD61vR xa1qJZOetK/Le1VtA4MPWtdtjO5ABM3edSspkdokqbL7cGo3winTfWaghbpKZTkaqtS3 OIH7mRFmY+mTdt9xNu4VNRpNA7m3O6+cTduZjwXL3MUdobfjv3B47rJPrESqj1wPF2v9 73hPYB0WFN5akmWAmVk79yVS+kKfCmAwafcz8LywLxqtVRSjMGE5CFGIiJE3Iw70+I23 19kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777921730; x=1778526530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=k0Z25Ri0qsZf4kdu4iu99TPanG49TW6penprmyqGHx0=; b=lwMSn7Dcp94sageEKaDSZszTNvnIDD1H/feO7OXX0Xj+KauseFw0JnKN/vwOJB4D58 eM39rd+PAouEQoJ2Pdp/OlxRRU64souE4y6EwYLytewSSkDI//qzT19fsGp9a8RRx5TS n0uh1AH+a8TozbdgAeiAhwF0+MSB/XaG01nBQDd21tbi37r5ygKBL+m4rYSd4na922Mr J9JnAVYQCljrHwdZ2wxA03LuH7latQeGrVNlE+jTVdR9uuFFsT5/7AKHZgSRU1wH4ogD qKsJcg6aBcPnrJetxmUHl62y1FOXbMjmfmG9EH5aQrX/Mwj9vsLx5mAY5Dk9+60Bu4Gu 5pNQ== X-Forwarded-Encrypted: i=1; AFNElJ9pycJ/sQfaQYqmeP2W6CdyRzIWDHXtn9Fobs6zJdW0wCRENnRhwHvlRpBJ2egJtJG14XpOlJEk086mr+w=@vger.kernel.org X-Gm-Message-State: AOJu0YyPXXRPtkVUxUMzXZ5j+ewoKlBUqq+1UV1EhK1+4OqIADSWItat h1QMY6yK2uvlEPNCYFHm4vdiB73Y1zyjdMP5FaYRC82DqFlt+dIuvZjAo4A2xd6g4rDNTZth7be i4zrQ2nfLc7lmK4V1K0EFetGayN+U7SK2FBHSQJkxVKPc9qscBPv1HY4jCoDSwjKlOPw= X-Gm-Gg: AeBDieuuEkqeRBZbkm9dGzkzbgmFlHFc6Urev4Ct8Oucq2Z3GJhVuc2x5HjkX+nbGnj ioxodeGjbpMJAoIPaX1SP/1QTahqMej80L6DKY0cwHmA8qfcIcJTPIeLHunw5l97PaOrchp+xSp WOOV9ArmHF8HPK8G/1DcMI6K2AsCb8bbXKnnIZL+2N/Qs9CEsz5MJ4os1yYEb0kOdUrIlo2R7Hi oMkyc4ijIdnaF1BtKI2tnampl8zsrRq8ey/aEqkFTEdabYNQrXvkiYutg+1E0ysplZ6A+i/7u4x 95p/UAdyBHwApt4GJMYru9f4K79NM46WGifYWd9LP2sjB/bah4F5ZXw78lWNpsMrq4Yb4aK45ib rmAIk27MWaBMMf092pwzWtC/rHnTt8SgihzzjA3I/uYY= X-Received: by 2002:a05:6a20:4321:b0:39b:8b8b:39ce with SMTP id adf61e73a8af0-3aa3b75d1d7mr67045637.28.1777921730358; Mon, 04 May 2026 12:08:50 -0700 (PDT) X-Received: by 2002:a05:6a20:4321:b0:39b:8b8b:39ce with SMTP id adf61e73a8af0-3aa3b75d1d7mr66994637.28.1777921729784; Mon, 04 May 2026 12:08:49 -0700 (PDT) Received: from localhost ([2601:1c0:5000:d5c:4ec8:83f5:8254:6891]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7ffbc8ee1csm10487520a12.25.2026.05.04.12.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 May 2026 12:08:49 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 16/16] drm/msm/a6xx: Allow IFPC with perfcntr stream Date: Mon, 4 May 2026 12:06:59 -0700 Message-ID: <20260504190751.61052-17-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260504190751.61052-1-robin.clark@oss.qualcomm.com> References: <20260504190751.61052-1-robin.clark@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=U9eiy+ru c=1 sm=1 tr=0 ts=69f8eec3 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=xqWC_Br6kY4A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=5obZvuzjGUYrwyXX1KsA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: CEKr1jgYcR64uhH0s1xtKDX81Ima4-Iy X-Proofpoint-GUID: CEKr1jgYcR64uhH0s1xtKDX81Ima4-Iy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA0MDE3NSBTYWx0ZWRfX25NFF9DVh0c7 yvl9XkZwHKCFmkiVN0mlPYUKHkFujXeskk402oyX0YViPVMUPUC4eE7wfIO4hXR+MZSDKs9iGAI 1gYn038alglTYxYvBW3JzRGy3RIJJGtf9p0S2u6jzgV/AIQV6w86QESatrUn4Ii1ktKrgInPBH0 +AgAL2Jo1KBj+f/b2uxzRUChx+53mA9pSdHNJYHkhZe+t+7hTqB+g3LK0YRHUOO00QpjQoI3dQe s5JCeo2rT4laxsw4gCnnw7qw0iwrZLYrOd2HPbyw9V2rl+EhOkhMWC/agXEcwnWATA6N7yfhMhd iYatETgCMAqbpjisnE3nhqDGv3ZQbcTS0k+LfWi96118BLSSHsyoiYS7iH0BBfOEXU0LDcmhN1N aP81NIW8kOnqQLB6lPEQaLc3LRyHT4Fnjd7dz/+6xOtqAeHFkoMrjtxCk4YNamJ9WS/az7SWP0I 1iTc0DCZ6tsOls+Aw4g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-04_05,2026-04-30_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 adultscore=0 phishscore=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605040175 Now that the dynamic pwrup reglist has SEL reg values to restore appended, so that SEL regs are restored on IFPC exit, we can stop completely disabling IFPC while global counter sampling is active. To accomplish this, we re-use sysprof_setup() with a force_on param to inhibit IFPC specifically while the counter regs are being read, while leaving IFPC enabled the rest of the time. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 10 ++-------- drivers/gpu/drm/msm/msm_perfcntr.c | 8 ++++++++ drivers/gpu/drm/msm/msm_submitqueue.c | 2 +- 5 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index aba08fb76249..3fe0f1cda46a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2034,9 +2034,9 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, return irq; } -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu) +void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on) { - bool sysprof = msm_gpu_sysprof_no_ifpc(gpu); + bool sysprof = msm_gpu_sysprof_no_ifpc(gpu) | force_on; struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index f3cc9478b079..eecc71843bed 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -280,7 +280,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu); +void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on); void a6xx_preempt_init(struct msm_gpu *gpu); void a6xx_preempt_hw_init(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 67f1e84eb631..93124c032dd4 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -93,7 +93,7 @@ struct msm_gpu_funcs { * for cmdstream that is buffered in this FIFO upstream of the CP fw. */ bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); - void (*sysprof_setup)(struct msm_gpu *gpu); + void (*sysprof_setup)(struct msm_gpu *gpu, bool force_on); /* Configure perfcntr SELect regs: */ void (*perfcntr_configure)(struct msm_gpu *gpu, struct msm_ringbuffer *ring, @@ -378,13 +378,7 @@ msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu) static inline bool msm_gpu_sysprof_no_ifpc(struct msm_gpu *gpu) { - /* - * For now, this is the same condition as disabling perfcntr clears - * on context switch. But once kernel perfcntr IFPC support is in - * place, we will only need to disable IFPC for legacy userspace - * setting SYSPROF param. - */ - return msm_gpu_sysprof_no_perfcntr_zap(gpu); + return refcount_read(&gpu->sysprof_active) > 1; } /* diff --git a/drivers/gpu/drm/msm/msm_perfcntr.c b/drivers/gpu/drm/msm/msm_perfcntr.c index 39bec201d5c9..d8ec65fa25f0 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.c +++ b/drivers/gpu/drm/msm/msm_perfcntr.c @@ -256,6 +256,10 @@ sample_worker(struct kthread_work *work) return; } + /* Inhibit IFPC while accessing registers: */ + if (gpu->funcs->sysprof_setup) + gpu->funcs->sysprof_setup(gpu, true); + if (gpu->funcs->perfcntr_flush) gpu->funcs->perfcntr_flush(gpu); @@ -290,6 +294,10 @@ sample_worker(struct kthread_work *work) } } + /* Re-enable IFPC: */ + if (gpu->funcs->sysprof_setup) + gpu->funcs->sysprof_setup(gpu, false); + smp_store_release(&stream->fifo.head, head); wake_up_all(&stream->poll_wq); } diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c index a58fe41602c6..1a5a77b28016 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -42,7 +42,7 @@ int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sy /* Some gpu families require additional setup for sysprof */ if (gpu->funcs->sysprof_setup) - gpu->funcs->sysprof_setup(gpu); + gpu->funcs->sysprof_setup(gpu, false); ctx->sysprof = sysprof; -- 2.54.0