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Mon, 04 May 2026 12:08:22 -0700 (PDT) Received: from localhost ([2601:1c0:5000:d5c:4ec8:83f5:8254:6891]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-364ec02ab2fsm12520021a91.14.2026.05.04.12.08.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 May 2026 12:08:21 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Akhil P Oommen , Rob Clark , Dmitry Baryshkov , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 03/16] drm/msm/adreno: Sync registers from mesa Date: Mon, 4 May 2026 12:06:46 -0700 Message-ID: <20260504190751.61052-4-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260504190751.61052-1-robin.clark@oss.qualcomm.com> References: <20260504190751.61052-1-robin.clark@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=APflyhIR c=1 sm=1 tr=0 ts=69f8eeaa cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=xqWC_Br6kY4A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=e5mUnYsNAAAA:8 a=SSmOFEACAAAA:8 a=EUspDBNiAAAA:8 a=vMjXctBndKc6M4jOp94A:9 a=-YkrfQbNLgtqXKMw:21 a=uKXjsCUrEbL0IQVhDsJ9:22 a=Vxmtnl_E_bksehYqCbjh:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA0MDE3NSBTYWx0ZWRfX9I16CMcdj6DY MzLB9y/cVCO7I6YcNcwNi4h4MVTDbJmItszXFm9AXnKAyAqxVP5deiYqTMuyxxY85aa8cKySl0k StQMS4KUsHbVkwHEoZEh/Z+1zA/cHeYemMa3J0wksBN/gxHwlzLIYyg2uszx0JMv6c9Fqwzm8+w dMYr1mw4/WrASY5J9LnzwJmhx4WD19X7ovsjOFrF4BceTA7viDjXho9M73W3FSZ2zYhI2Wt7acL 1H0iGiwsa5J2VfG63OxQU/WB/wJUAOwF8j3nnP0Sl41FiKmoFdmk9ypuAuA/j5nReMuhHoVgGDW ovkynXWo5wXv00teGSsGZSYcRxXsCViTdg2/+/yhNms0IdMpTAv4C6P8U9xDF1qSOH/fUBSXYwX QnxDZbwxJajkQljCyIM//4bE8Cv9D5Qz7lDG5R0iBSGe5Ou0f+DQKpxCl6oVlmH12I3nHHk+GEv eLD4K/NcvE5bIUlECig== X-Proofpoint-GUID: pJfPO0qOQVPexhAYHS1ZXQWkqH71CFPo X-Proofpoint-ORIG-GUID: pJfPO0qOQVPexhAYHS1ZXQWkqH71CFPo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-04_05,2026-04-30_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605040175 Most of the churn is just reworking the usage attribute on the mesa side. Sync from mesa commit 4d4a951ac622 ("fd: add a8xx perfcntr countables"). Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 16 +- drivers/gpu/drm/msm/registers/adreno/a3xx.xml | 8 +- drivers/gpu/drm/msm/registers/adreno/a5xx.xml | 141 +- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1300 +++++------ .../msm/registers/adreno/a6xx_descriptors.xml | 71 +- .../drm/msm/registers/adreno/a6xx_enums.xml | 3 + .../msm/registers/adreno/a8xx_descriptors.xml | 96 +- .../msm/registers/adreno/a8xx_perfcntrs.xml | 1929 +++++++++++++++++ .../msm/registers/adreno/adreno_common.xml | 42 + .../drm/msm/registers/adreno/adreno_pm4.xml | 50 +- 10 files changed, 2846 insertions(+), 810 deletions(-) create mode 100644 drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 79acae11154a..9a03684288d3 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -752,17 +752,13 @@ static int a5xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02); /* Disable L2 bypass in the UCHE */ - gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, lower_32_bits(adreno_gpu->uche_trap_base)); - gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, upper_32_bits(adreno_gpu->uche_trap_base)); - gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, lower_32_bits(adreno_gpu->uche_trap_base)); - gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, upper_32_bits(adreno_gpu->uche_trap_base)); + gpu_write64(gpu, REG_A5XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); + gpu_write64(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); /* Set the GMEM VA range (0 to gpu->gmem) */ - gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000); - gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000); - gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO, + gpu_write64(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN, 0x00100000); + gpu_write64(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX, 0x00100000 + adreno_gpu->info->gmem - 1); - gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) { @@ -1217,9 +1213,7 @@ static void a5xx_rbbm_err_irq(struct msm_gpu *gpu, u32 status) static void a5xx_uche_err_irq(struct msm_gpu *gpu) { - uint64_t addr = (uint64_t) gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_HI); - - addr |= gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_LO); + uint64_t addr = gpu_read64(gpu, REG_A5XX_UCHE_TRAP_LOG); dev_err_ratelimited(gpu->dev->dev, "UCHE | Out of bounds access | addr=0x%llX\n", addr); diff --git a/drivers/gpu/drm/msm/registers/adreno/a3xx.xml b/drivers/gpu/drm/msm/registers/adreno/a3xx.xml index 6717abc0a897..09c9606fc3e1 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a3xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a3xx.xml @@ -1330,11 +1330,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> - - + @@ -1420,7 +1416,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> - + diff --git a/drivers/gpu/drm/msm/registers/adreno/a5xx.xml b/drivers/gpu/drm/msm/registers/adreno/a5xx.xml index bd8df5945166..4af76b3750f7 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a5xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a5xx.xml @@ -1418,8 +1418,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> - - + @@ -1498,12 +1497,10 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> - - + - - + @@ -1555,20 +1552,14 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> - - - - - - - - + + + + - - - - + + @@ -1583,8 +1574,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> - - + @@ -1923,8 +1913,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> invalidates the LRZ buffer? (Or just the covered positions? --> - - + @@ -1933,8 +1922,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> is also divided by 8 (ie. covers 8x8 pixels) - - + @@ -2035,8 +2023,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set --> - - + @@ -2089,8 +2076,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set - - + stride of depth/stencil buffer @@ -2119,8 +2105,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set - - + @@ -2163,8 +2148,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set also for gmem->mem preserving tiling --> - - + @@ -2235,25 +2219,22 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set - - + - + - - + - - + @@ -2357,13 +2338,11 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set - - + - - + @@ -2423,8 +2402,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set - - + @@ -2475,7 +2453,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set - + @@ -2516,8 +2494,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set - - + @@ -2538,8 +2515,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set - - + @@ -2577,8 +2553,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set - - + @@ -2587,22 +2562,19 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set - - + - - + - - + @@ -2615,8 +2587,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set - - + diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml index 2309870f5031..3349c01646e1 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -10,19 +10,24 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + @@ -1321,7 +1326,7 @@ by a particular renderpass/blit. - + @@ -1331,13 +1336,13 @@ by a particular renderpass/blit. - + - + - + Configures the mapping between VSC_PIPE buffer and @@ -1370,7 +1375,7 @@ by a particular renderpass/blit. - + Seems to be a bitmap of which tiles mapped to the VSC pipe contain geometry. @@ -1381,7 +1386,7 @@ by a particular renderpass/blit. - + Has the size of data written to corresponding VSC_PRIM_STRM buffer. @@ -1389,7 +1394,7 @@ by a particular renderpass/blit. - + Has the size of data written to corresponding VSC pipe, ie. same thing that is written out to VSC_SIZE_BASE @@ -1397,7 +1402,7 @@ by a particular renderpass/blit. - + @@ -1428,29 +1433,22 @@ by a particular renderpass/blit. - - + + - - - - - - - - - - - - - - - - + + + + + + + + + @@ -1465,16 +1463,16 @@ by a particular renderpass/blit. - - + + - - + + @@ -1499,33 +1497,48 @@ by a particular renderpass/blit. - + + + - + - + - + - + + + + + + + + + + + + + + - + @@ -1534,7 +1547,7 @@ by a particular renderpass/blit. - + @@ -1543,16 +1556,16 @@ by a particular renderpass/blit. - + - + - + @@ -1572,17 +1585,18 @@ by a particular renderpass/blit. TODO: what about gen2 (a640)? --> - - - - - - - - + + + + + + + + + @@ -1590,49 +1604,49 @@ by a particular renderpass/blit. - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + @@ -1640,8 +1654,8 @@ by a particular renderpass/blit. - - + + @@ -1667,19 +1681,19 @@ by a particular renderpass/blit. - - - + + + - - - + + + - + @@ -1738,10 +1752,10 @@ by a particular renderpass/blit. - + - + @@ -1778,7 +1792,7 @@ by a particular renderpass/blit. - + @@ -1795,7 +1809,7 @@ by a particular renderpass/blit. - + @@ -1808,16 +1822,16 @@ by a particular renderpass/blit. - - + + - - + + @@ -1835,15 +1849,15 @@ by a particular renderpass/blit. - - - + + + - - - - - + + + + + @@ -1860,30 +1874,53 @@ by a particular renderpass/blit. - + - + - + - + - - + + + + + + + + + + + + + + + + + + + + + + - - + + + + + @@ -1893,45 +1930,59 @@ by a particular renderpass/blit. - + + + + + + + + + - - + + + + + - - + + + + + - - + + - - + + - - + + @@ -1966,24 +2017,23 @@ by a particular renderpass/blit. - + - - + + - + The total size of the LRZ image array (not including fast clear buffer), used as a stride for double buffering used with concurrent binning. - - - - + + + @@ -1995,28 +2045,28 @@ by a particular renderpass/blit. - - + + - - + + - - + + - + - - + + - + - - + + - + @@ -2082,8 +2132,8 @@ by a particular renderpass/blit. - - + + LUT used to convert quality buffer values to HW shading rate values. An array of 4-bit values. @@ -2128,32 +2178,32 @@ by a particular renderpass/blit. - + - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + @@ -2180,10 +2230,10 @@ by a particular renderpass/blit. --> - - + + - + @@ -2197,7 +2247,7 @@ by a particular renderpass/blit. - + @@ -2206,26 +2256,26 @@ by a particular renderpass/blit. - + - + - - - - - + + + + + - + @@ -2236,7 +2286,7 @@ by a particular renderpass/blit. - + @@ -2248,16 +2298,16 @@ by a particular renderpass/blit. - + - + - + @@ -2277,7 +2327,7 @@ by a particular renderpass/blit. - + @@ -2289,11 +2339,11 @@ by a particular renderpass/blit. - + - + @@ -2316,7 +2366,7 @@ by a particular renderpass/blit. - + @@ -2330,12 +2380,12 @@ by a particular renderpass/blit. - + - + @@ -2383,16 +2433,16 @@ by a particular renderpass/blit. - - - - + + + + - + @@ -2401,12 +2451,12 @@ by a particular renderpass/blit. - + - + - + @@ -2422,23 +2472,23 @@ by a particular renderpass/blit. - + - + - - - - + + + + - - + + - + - + - + @@ -2498,41 +2548,41 @@ by a particular renderpass/blit. - - + + - + - + - + - - + + - + - - - + + + - - + + - + - + @@ -2541,23 +2591,23 @@ by a particular renderpass/blit. - - + + - - + + - + - - - - + + + + @@ -2567,7 +2617,7 @@ by a particular renderpass/blit. - + @@ -2595,7 +2645,7 @@ by a particular renderpass/blit. - + @@ -2637,17 +2687,17 @@ by a particular renderpass/blit. - + - + - + @@ -2656,16 +2706,25 @@ by a particular renderpass/blit. + + + + + + + + + - - + + - + @@ -2683,7 +2742,8 @@ by a particular renderpass/blit. - + + @@ -2693,13 +2753,13 @@ by a particular renderpass/blit. These show up in a6xx gen3+ but so far haven't found an example of blob writing non-zero: --> - - - - + + + + - - + + @@ -2731,28 +2791,28 @@ by a particular renderpass/blit. - - - + + + - - - + + + - - + + - - + + - - - - + + + + - + @@ -2821,7 +2881,7 @@ by a particular renderpass/blit. - + @@ -2847,7 +2907,7 @@ by a particular renderpass/blit. - + @@ -2860,17 +2920,17 @@ by a particular renderpass/blit. - - - + + + - - - + + + - - - + + + @@ -2878,17 +2938,17 @@ by a particular renderpass/blit. - - - + + + - - - + + + - - - + + + @@ -2897,19 +2957,19 @@ by a particular renderpass/blit. - - - - + + + + - + - - + + @@ -2949,14 +3009,14 @@ by a particular renderpass/blit. - - - - - - - - + + + + + + + + @@ -2973,20 +3033,20 @@ by a particular renderpass/blit. - + Packed array of a6xx_varying_interp_mode - + Packed array of a6xx_varying_ps_repl_mode - + Packed array of a6xx_varying_interp_mode - + Packed array of a6xx_varying_ps_repl_mode @@ -2995,12 +3055,12 @@ by a particular renderpass/blit. - + - + @@ -3034,8 +3094,8 @@ by a particular renderpass/blit. - - + + @@ -3047,8 +3107,8 @@ by a particular renderpass/blit. - - + + @@ -3097,13 +3157,13 @@ by a particular renderpass/blit. - - - + + + - - - + + + @@ -3124,8 +3184,8 @@ by a particular renderpass/blit. - - + + - - + + @@ -3253,7 +3313,7 @@ by a particular renderpass/blit. - + @@ -3287,9 +3347,12 @@ by a particular renderpass/blit. - - - + + + + + + - - + + @@ -3324,31 +3387,31 @@ by a particular renderpass/blit. - - - - + + + + - - - - + + + + - - + + - + size in vec4s of per-primitive storage for gs. TODO: not actually in VPC - - + + - - + + @@ -3426,18 +3489,18 @@ by a particular renderpass/blit. - + - + - + This is the ID of the current patch within the @@ -3450,20 +3513,20 @@ by a particular renderpass/blit. - + - - + + - + - + - + @@ -3474,7 +3537,7 @@ by a particular renderpass/blit. - + @@ -3482,14 +3545,14 @@ by a particular renderpass/blit. - - - + + + - + @@ -3502,14 +3565,14 @@ by a particular renderpass/blit. - + - + @@ -3549,10 +3612,12 @@ by a particular renderpass/blit. --> - - - + + + + + @@ -3580,7 +3645,7 @@ by a particular renderpass/blit. - + - - + + @@ -3623,7 +3688,7 @@ by a particular renderpass/blit. an extra varying after, but with a lower OUTLOC position. If present, psize is last, preceded by position. --> - + @@ -3712,20 +3777,20 @@ by a particular renderpass/blit. - - - - - - - - - + + + + + + + + + - + @@ -3735,32 +3800,32 @@ by a particular renderpass/blit. the maximum size of local storage should be: 64 (wavesize) * 64 (SP_HS_CNTL_1) * 4 = 16k --> - - + + - - - - - - - - - + + + + + + + + + - + - - + + @@ -3768,7 +3833,7 @@ by a particular renderpass/blit. - + @@ -3778,24 +3843,24 @@ by a particular renderpass/blit. - - - - - - - - - + + + + + + + + + - + - + Normally the size of the output of the last stage in dwords. It should be programmed as follows: @@ -3809,14 +3874,14 @@ by a particular renderpass/blit. doesn't matter in practice. - + - + - + @@ -3825,7 +3890,7 @@ by a particular renderpass/blit. - + @@ -3835,15 +3900,15 @@ by a particular renderpass/blit. - - - - - - - - - + + + + + + + + + @@ -3859,7 +3924,7 @@ by a particular renderpass/blit. - + @@ -3878,16 +3943,15 @@ by a particular renderpass/blit. and so one pixel's value is always unused. - - - - - - + + + + + @@ -3897,12 +3961,12 @@ by a particular renderpass/blit. - - + + - + @@ -3913,7 +3977,7 @@ by a particular renderpass/blit. - + @@ -3923,17 +3987,17 @@ by a particular renderpass/blit. - + - + - + per MRT @@ -3941,7 +4005,7 @@ by a particular renderpass/blit. - + @@ -3950,7 +4014,7 @@ by a particular renderpass/blit. - + @@ -3967,7 +4031,7 @@ by a particular renderpass/blit. - + @@ -3981,7 +4045,7 @@ by a particular renderpass/blit. - + @@ -3993,21 +4057,21 @@ by a particular renderpass/blit. - + - + - + - + @@ -4025,7 +4089,7 @@ by a particular renderpass/blit. - + If 0 - all 32k of shared storage is enabled, otherwise @@ -4045,29 +4109,29 @@ by a particular renderpass/blit. - - - - - - - - - - - - + + + + + + + + + + + + - + - + @@ -4104,10 +4168,10 @@ by a particular renderpass/blit. - - - - + + + + @@ -4118,13 +4182,13 @@ by a particular renderpass/blit. - + - + @@ -4134,9 +4198,9 @@ by a particular renderpass/blit. - - - + + + @@ -4192,7 +4256,7 @@ by a particular renderpass/blit. - + - + - + - - + + - + - + - + @@ -4259,8 +4323,8 @@ by a particular renderpass/blit. - - + + @@ -4268,7 +4332,14 @@ by a particular renderpass/blit. - + + + When this bit is enabled, new waves may be unlocked once + all invocations have signaled they don't need local + memory anymore using (eolm)nop. + + + @@ -4333,7 +4404,7 @@ by a particular renderpass/blit. - + - - - - + + + + - + + - - + @@ -4387,6 +4458,11 @@ by a particular renderpass/blit. + + + + + @@ -4395,24 +4471,26 @@ by a particular renderpass/blit. badly named or the functionality moved in a6xx. But downstream kernel calls this "a6xx_sp_ps_tp_2d_cluster" --> - - + + - - + + - - + + - - + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + - - + + + - - + + + - + + + - + - - - - - - + + + + + + - + - + - - - - + + + + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - - - + + + @@ -4690,7 +4774,7 @@ by a particular renderpass/blit. - + @@ -4711,7 +4795,7 @@ by a particular renderpass/blit. - + @@ -4723,7 +4807,7 @@ by a particular renderpass/blit. - + @@ -4731,7 +4815,7 @@ by a particular renderpass/blit. - + @@ -4750,7 +4834,7 @@ by a particular renderpass/blit. - + This register clears pending loads queued up by CP_LOAD_STATE6. Each bit resets a particular kind(s) of @@ -4790,7 +4874,7 @@ by a particular renderpass/blit. - + This register clears pending loads queued up by CP_LOAD_STATE6. Each bit resets a particular kind(s) of @@ -4813,7 +4897,7 @@ by a particular renderpass/blit. - + This register clears pending loads queued up by CP_LOAD_STATE6. Each bit resets a particular kind(s) of @@ -4829,16 +4913,16 @@ by a particular renderpass/blit. - - + + - - + + - - + + - + Shared constants are intended to be used for Vulkan push constants. When enabled, 8 vec4's are reserved in the FS diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml index 56cfaff614a4..08bc37f29a6f 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml @@ -45,19 +45,21 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> - + Texture constant dwords - - - - - + + + + + + - - + + + probably for D3D structured UAVs, normally set to 1 - - + + - + Pitch in bytes (so actually stride) - + @@ -94,15 +97,15 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> layer size at the point that it stops being reduced moving to higher (smaller) mipmap levels --> - - + + - - + + - + - + + + + + - + + - + + + + - + + - + - - + + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml index 81538831dc19..b44946f36fae 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml @@ -328,6 +328,9 @@ to upconvert to 32b float internally? + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml b/drivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml index edcbdb3b6921..d119d021446c 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml @@ -39,76 +39,92 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> - + Texture memobj dwords - + + for type TEX_BUFFER + - + + - + + for type TEX_BUFFER, probably for D3D structured UAVs, normally set to 1 + - - - + + + + - - - - + + + + - - - - + + + + - + - + - + - - - - + + + + + + + + + + - - - + + + - - - - - - + + + + + + - - + + + + + + - + - - + + - + - + - - + + diff --git a/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml b/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml new file mode 100644 index 000000000000..a5bb44f76956 --- /dev/null +++ b/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml @@ -0,0 +1,1929 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml b/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml index 79d204f1e400..195cee078357 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml @@ -14,6 +14,27 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + + + + TEX_MEMOBJ descriptor types. These are used + to mark fields that only apply to certain + descriptor types, and potentially overlap + with fields in other types. + + + + + + + Additional descriptor types not part of + TEX_MEMOBJ. These are described by their + own toplevel domain. + + + + + @@ -409,4 +430,25 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + + + + + + + + + + + + + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml index 51e9c94f5e37..f185b541aa70 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml @@ -152,6 +152,8 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + + @@ -1095,7 +1097,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + @@ -1275,8 +1277,15 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + + @@ -1469,6 +1478,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) + @@ -1476,7 +1486,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + @@ -2055,28 +2065,20 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - Executes the following DWORDs of commands if the dword at ADDR0 - is not equal to 0 and the dword at ADDR1 is less than REF - (signed comparison). + Executes the following DWORDs of commands if the dword + at BOOL_ADDR is not equal to 0 and the the timestamp + value ACTIVE_TIMESTAMP is ahead of the value fetched + from TIMESTAMP_ADDR. + + The timestamp comparision is an unsigned compare with + wraparound, ie: + + (ACTIVE_TIMESTAMP - *TIMESTAMP_ADDR) < 0x80000000 - - - - - - - - - - - - - - - - - - + + + + -- 2.54.0