From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9880938C427 for ; Mon, 4 May 2026 19:08:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777921721; cv=none; b=Nkao8+oMPxpNaLYxRZFviCfczUHZxBdipCR+edxQHLrmDVr2A/xxJpFPPStAmn71V3iM0JCxbGdomL86898ttCYq/U92axnqdOcTgymWRrwADC8EXxxjOzI2agXYWmrLT72BN+jmliPomiMxX7a8dMX+urjVWpKlHXS0oFTX1/I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777921721; c=relaxed/simple; bh=nf/AzQJzAwD5Wdqnd6VCCPR5ecVd2qygEvoiPvLJ7Vg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B5XS/piGF4mKkRleHWk/QNpOuhk1iCIGGAKtrQCOAz00aLHvSNciG8H74L9uNzb9NkPe9Owt23yrn7boeKDF9nvEE4P9hjB+yO8Z/zO2wZgYm1ZEoyvMgEk50LO0VyrM/aXaCEVVGhSpfMj24SkScx0DwGEZ7fQ1ZN7rToEnzC8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cf2cM+FH; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=UWgjTxIf; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cf2cM+FH"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="UWgjTxIf" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 644IDtNY748896 for ; Mon, 4 May 2026 19:08:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=ZFtTLmOQAzj qHoC3Fafdx5s7yem/Cv9ClA1WpeTUDMw=; b=cf2cM+FH6ACHDWi0ShgqF+Lpf09 /By6SaAMHztFm2ApbaYtnaM15NdXB/euzLVNLIsKq2uH5WTxZeUrUyf4zipqYHW0 0x7wHXlyzvH9NWr3LuR6siIqrouAxjsLSCgkGuyOKRcBiLF2WuZfi3Ih+YgQQBm4 cD7UXceANKX9CQrXQBNlKb0+PA26eB0Va1U8nbQekbE4YmW39mXnpWTyzuPx8Fc3 4ZyC0iOLR0mzDLAyMSuG41W1kPCwQs6MPh0aDkQiy4nE5FkTxpysu5WrSKTb5w/H 6THLiqNr9OGWLUrZrBH0wuWH5pW70GJ6v3Vrr2BqgzYLfOcZ52Y+FRXrYfw== Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dxscf1xe4-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 04 May 2026 19:08:36 +0000 (GMT) Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-c6e24ee93a6so2828283a12.0 for ; Mon, 04 May 2026 12:08:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1777921715; x=1778526515; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZFtTLmOQAzjqHoC3Fafdx5s7yem/Cv9ClA1WpeTUDMw=; b=UWgjTxIfI4lpjAUTsW+H2prg1g3+0ZkasMwxy9s6836UUKvXpXh1YiDXTnitsBXP3K rZxZ68yuxe+v4qyZB0ot5lDI35aK0WKYY7H+D1aXxdHkbuIxRB55Eq+MdNdVQeDAGXFM KrJC+lSUmwmL/BF/ySP+ITIHKgbLJxjTwBQ0bgpP/oy8KoLq5YSx1D2qeMIIevRsPJK8 KGdn0Hc/swQj6ycp+1CUuA2o0gvnl1oIT+LvjOzFE8LhHPzQyv/xulCOiADok8nYcfOU Ik+d8f+2sGZUy0iSvm1KtStBBE8UzFs3sM5hSjyyCYh05jMIa9JT35mlXXK7G/UH99UL sgwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777921715; x=1778526515; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ZFtTLmOQAzjqHoC3Fafdx5s7yem/Cv9ClA1WpeTUDMw=; b=MpvpApAF9RAYxQE5DhwivA1FaWIVev8nIBPc5F8NsMFfvz8rBhKpoEYs91k87OH4is fSBLVZHLqweWaTd1RKjkoCC35Xp16Oi6I/PdGCC4T/Jc/Qsxto1mPiN2Hf0eQyA3tjNv +K7FSLx19MWg5AxXSZHU/lTx+cBgsrKCOBcWsO3hNfGgifFh38dHWowM3260rlC03j+v Z+SnuMySPhuM+C0G4RX4PtqYrMz1qqMlDVIUYcrVj5iy+1U5Z0s3pQC3sa/8hSos8oRl fjcwPrcy+T11nY3KqHiuwRzVshXQt27CNJ42MMZi9prwbXMKkFanWP2NJuoyZ6mk+dlg QzIA== X-Forwarded-Encrypted: i=1; AFNElJ8hZQzGZvDpawgJueL/QtueBfvW+oL1dnPTMc88Enb3KDKVtG2d02FG7txATHic3fGXp0Fg7LbYNElJzTc=@vger.kernel.org X-Gm-Message-State: AOJu0YxKhSmzfiRGFrIMdFZzQGrXILowq2g9fL47drjVMc61uqf9Url3 rCA5Lb66pADzjk8oB/ITRGKNG/RiUisFkyeTafRRS0oJKfbe5WxOLzBibEx7QwFhQkFP6alIt2T qzPsmi4dsBYNGe9eZrgIBfKA8cC1FEkGIxMUrCqJbKrPxTQfT0PbmZW3Et6fMTLO3VhM= X-Gm-Gg: AeBDiev0/ljI8lLsLgxlt7nrc9H8k6hpcNevsGf2IH+MvNy4pn4m94H77yLXZEmamv3 zhUaRWLVLLWsswI9+rEI/7EOXLROG5xW1VPk3BHtMi55Yx9hQzSSL/Ef/JwIQqMYiaI+CEsTfn/ cPtuUHNtt6KgNBs1OOwAMWJ80Ib2s1mzPz5XeB0htPzr5Q8BBj+UZ8avh6UHLBjnXwKvX0ClvBg CHeYVrOI3a1grBXy/C/rU0SIo7NjT4fMMoevctX1qNKqfD/eYYbyWs+iwyUsJqhcnJggWLlHM5+ jO8OFZfe/nAigzdSsonP+YVoyVHmDKRC8zE99+ukqykQ15/o/cv8MR+Rp+iCeZSL2uppmQf5HVT E2kf18tb0jCcWwF5c4XrLgLTPLqoQbdvtMQiO+yzblHs= X-Received: by 2002:a05:6a20:4305:b0:39b:ca34:96e3 with SMTP id adf61e73a8af0-3a9f77bd7a2mr567274637.37.1777921715031; Mon, 04 May 2026 12:08:35 -0700 (PDT) X-Received: by 2002:a05:6a20:4305:b0:39b:ca34:96e3 with SMTP id adf61e73a8af0-3a9f77bd7a2mr567242637.37.1777921714478; Mon, 04 May 2026 12:08:34 -0700 (PDT) Received: from localhost ([2601:1c0:5000:d5c:4ec8:83f5:8254:6891]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7ffbb05798sm10380209a12.0.2026.05.04.12.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 May 2026 12:08:34 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 08/16] drm/msm/a6xx: Add yield & flush helper Date: Mon, 4 May 2026 12:06:51 -0700 Message-ID: <20260504190751.61052-9-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260504190751.61052-1-robin.clark@oss.qualcomm.com> References: <20260504190751.61052-1-robin.clark@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=BcvoFLt2 c=1 sm=1 tr=0 ts=69f8eeb4 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=xqWC_Br6kY4A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=7a4_7rcHm0II5uOVc2AA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA0MDE3NSBTYWx0ZWRfX6qbqVOupF7mH ktrsmqG3lSl9Ob+Ca9q/+gEJOkrAkrgOY+SEEpQzWwt7zZgjD57hXI62JZj3w4mkrzYGCocIZgJ 4lBQaYG6/Bjmadqik7CmtUK0GwxmxglyqFBWTdb2eHp0APdD2fmBqorEMyy1XOa/k7oA70AuhR9 hKXFPxc+J6lEGmK42OxOTOWvcd3ROP7ajkVWb3jhGz8oXwJGSGg1tZlsWRxn/E9twXXyTDd6M2Q u0N8XH+FsUd48PYrdfM2AK1ARlCgFdj17Qak0/w6eJTvV0uOTZ3XqstE8OXmo8h7jBNqTqDjESN DwmSOHedcW0cAKGvobBmiS3+zcCv+/0XIYUsiPgTI4Seg4YbLv363kaBKC1Q0koKY/oFtfCKWvr Ww2eVLH5jllNIIUETi6bBU5xd5Uo6Qbvb0WXvvLlrwYlIG1WNVIupsF3Lv5CPBsjF3VdGnuIzbo 4BhiGakaaoTryFDSmJg== X-Proofpoint-ORIG-GUID: 2-_Unh41lv1SQWTFlkLWZp-dFkx_qz9u X-Proofpoint-GUID: 2-_Unh41lv1SQWTFlkLWZp-dFkx_qz9u X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-04_05,2026-04-30_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605040175 It's a common pattern, needing to insert a yield packet before flushing the rb. And we'll need this once again for configuring perfcntr SEL regs. So add a helper. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 55 +++++++++++++-------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 10 +---- 3 files changed, 28 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 71f54ab5425d..415902f6e5d7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -189,6 +189,30 @@ void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) spin_unlock_irqrestore(&ring->preempt_lock, flags); } +void +a6xx_flush_yield(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +{ + /* If preemption is enabled */ + if (gpu->nr_rings > 1) { + /* Yield the floor on command completion */ + OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); + + /* + * If dword[2:1] are non zero, they specify an address for + * the CP to write the value of dword[3] to on preemption + * complete. Write 0 to skip the write + */ + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + /* Data value - not used if the address above is 0 */ + OUT_RING(ring, 0x01); + /* generate interrupt on preemption completion */ + OUT_RING(ring, 0x00); + } + + a6xx_flush(gpu, ring); +} + static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, u64 iova) { @@ -597,28 +621,9 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) OUT_PKT7(ring, CP_SET_MARKER, 1); OUT_RING(ring, 0x100); /* IFPC enable */ - /* If preemption is enabled */ - if (gpu->nr_rings > 1) { - /* Yield the floor on command completion */ - OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); - - /* - * If dword[2:1] are non zero, they specify an address for - * the CP to write the value of dword[3] to on preemption - * complete. Write 0 to skip the write - */ - OUT_RING(ring, 0x00); - OUT_RING(ring, 0x00); - /* Data value - not used if the address above is 0 */ - OUT_RING(ring, 0x01); - /* generate interrupt on preemption completion */ - OUT_RING(ring, 0x00); - } - - trace_msm_gpu_submit_flush(submit, adreno_gpu->funcs->get_timestamp(gpu)); - a6xx_flush(gpu, ring); + a6xx_flush_yield(gpu, ring); /* Check to see if we need to start preemption */ if (adreno_is_a8xx(adreno_gpu)) @@ -958,15 +963,7 @@ static int a7xx_preempt_start(struct msm_gpu *gpu) a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL); - /* Yield the floor on command completion */ - OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); - OUT_RING(ring, 0x00); - OUT_RING(ring, 0x00); - OUT_RING(ring, 0x00); - /* Generate interrupt on preemption completion */ - OUT_RING(ring, 0x00); - - a6xx_flush(gpu, ring); + a6xx_flush_yield(gpu, ring); return a6xx_idle(gpu, ring) ? 0 : -EINVAL; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index eb431e5e00b1..99c3e55f5ca8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -317,6 +317,7 @@ void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_ void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert); int a6xx_fenced_write(struct a6xx_gpu *gpu, u32 offset, u64 value, u32 mask, bool is_64b); void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); +void a6xx_flush_yield(struct msm_gpu *gpu, struct msm_ringbuffer *ring); int a6xx_zap_shader_init(struct msm_gpu *gpu); void a8xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index e022c9a162a4..124d315b2469 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -488,15 +488,7 @@ static int a8xx_preempt_start(struct msm_gpu *gpu) a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL); - /* Yield the floor on command completion */ - OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); - OUT_RING(ring, 0x00); - OUT_RING(ring, 0x00); - OUT_RING(ring, 0x00); - /* Generate interrupt on preemption completion */ - OUT_RING(ring, 0x00); - - a6xx_flush(gpu, ring); + a6xx_flush_yield(gpu, ring); return a8xx_idle(gpu, ring) ? 0 : -EINVAL; } -- 2.54.0