[PATCH v6 3/3] i2c: designware: Support of controller with IC_EMPTYFIFO_HOLD_MASTER disabled

Benoît Monin
2026-01-30T15:52:46Z

If IC_EMPTYFIFO_HOLD_MASTER_EN parameter is 0, "Stop" and "Repeated Start"
bits in command register do not exist, thus it is impossible to send
several consecutive write messages in a single hardware batch. The
existing implementation worked with such configuration incorrectly:
all consecutive write messages are joined into a single message without
any Start/Stop or Repeated Start conditions. For example, the following
command:

i2ctransfer -y 0 w1@0x55 0x00 w1@0x55 0x01

does the same as

i2ctransfer -y 0 w2@0x55 0x00 0x01

In i2c_dw_msg_is_valid(), we ensure that we do not have such sequence
of messages requiring a RESTART, aborting the transfer on controller
that cannot emit them explicitly.

This behavior is activated by compatible entries because the state of
the IC_EMPTYFIFO_HOLD_MASTER_EN parameter cannot be detected at runtime.
The new flag emptyfifo_hold_master reflects the state of the parameter,
it is set to true for all controllers except those found in Mobileye
SoCs. For now, the controllers in Mobileye SoCs are the only ones known
to need the workaround. The behavior of the driver is left unmodified
for other controllers.

There is another possible problem with this controller configuration:
When the CPU is putting commands to the FIFO, this process must not be
interrupted because if FIFO buffer gets empty, the controller finishes
the I2C transaction and generates STOP condition on the bus.

If we continue writing the remainder of the message to the FIFO, the
controller will start emitting a new transaction with those data. This
turns a single message into multiple I2C transactions. To protect against
FIFO underrun, two changes are done:

First we flag the interrupt with IRQF_NO_THREAD, to prevent it from
running in a thread on PREEMPT-RT kernel. This ensures that we are
not interrupted when filling the FIFO as it is very time-senstive. For
example, being preempted after writing a single byte in the FIFO with
a 1MHz bus gives us only 18µs before an underrun. DMA would allow us
to keep the interrupt threaded but it is not available on Mobileye SoC
for I2C.

Second in i2c_dw_process_transfer(), we abort if a STOP is detected
while a read or a write is in progress. This can occur when processing
a message larger than the FIFO. In that case the message is processed in
parts, and rely on the TX EMPTY interrupt to refill the FIFO when it gets
below a threshold. If servicing this interrupt is delayed for too long,
it can trigger a FIFO underrun, thus an unwanted STOP.

Originally-by: Dmitry Guzman <dmitry.guzman@mobileye.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
drivers/i2c/busses/i2c-designware-common.c | 20 ++++++++++++++++++++
drivers/i2c/busses/i2c-designware-core.h | 3 +++
drivers/i2c/busses/i2c-designware-master.c | 18 ++++++++++++++++++
drivers/i2c/busses/i2c-designware-platdrv.c | 1 +
4 files changed, 42 insertions(+)

diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c
index 64654dabbb21..4dc57fd56170 100644
--- a/drivers/i2c/busses/i2c-designware-common.c
+++ b/drivers/i2c/busses/i2c-designware-common.c
@@ -492,6 +492,12 @@ int i2c_dw_fw_parse_and_configure(struct dw_i2c_dev *dev)

dev->clk_freq_optimized = device_property_read_bool(device, "snps,clk-freq-optimized");

+ /* Mobileye controllers do not hold the clock on empty FIFO */
+ if (device_is_compatible(device, "mobileye,eyeq6lplus-i2c"))
+ dev->emptyfifo_hold_master = false;
+ else
+ dev->emptyfifo_hold_master = true;
+
i2c_dw_adjust_bus_speed(dev);

if (is_of_node(fwnode))
@@ -918,6 +924,20 @@ int i2c_dw_probe(struct dw_i2c_dev *dev)
else
irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;

+ /*
+ * The first writing to TX FIFO buffer causes transmission start.
+ * If IC_EMPTYFIFO_HOLD_MASTER_EN is not set, when TX FIFO gets
+ * empty, I2C controller finishes the transaction. If writing to
+ * FIFO is interrupted, FIFO can get empty and the transaction will
+ * be finished prematurely. FIFO buffer is filled in IRQ handler,
+ * but in PREEMPT_RT kernel IRQ handler by default is executed
+ * in thread that can be preempted with another higher priority
+ * thread or an interrupt. So, IRQF_NO_THREAD flag is required in
+ * order to prevent any preemption when filling the FIFO.
+ */
+ if (!dev->emptyfifo_hold_master)
+ irq_flags |= IRQF_NO_THREAD;
+
ret = i2c_dw_acquire_lock(dev);
if (ret)
return ret;
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index a49263a36023..9d8d104cc391 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -260,6 +260,8 @@ struct reset_control;
* @clk_freq_optimized: if this value is true, it means the hardware reduces
* its internal clock frequency by reducing the internal latency required
* to generate the high period and low period of SCL line.
+ * @emptyfifo_hold_master: true if the controller acting as master holds
+ * the clock when the Tx FIFO is empty instead of emitting a stop.
*
* HCNT and LCNT parameters can be used if the platform knows more accurate
* values than the one computed based only on the input clock frequency.
@@ -318,6 +320,7 @@ struct dw_i2c_dev {
struct i2c_bus_recovery_info rinfo;
u32 bus_capacitance_pF;
bool clk_freq_optimized;
+ bool emptyfifo_hold_master;
};

#define ACCESS_INTR_MASK BIT(0)
diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c
index 73d9347a6a08..de929b91d5ea 100644
--- a/drivers/i2c/busses/i2c-designware-master.c
+++ b/drivers/i2c/busses/i2c-designware-master.c
@@ -652,6 +652,14 @@ static void i2c_dw_process_transfer(struct dw_i2c_dev *dev, unsigned int stat)
if (stat & DW_IC_INTR_TX_EMPTY)
i2c_dw_xfer_msg(dev);

+ /* Abort if we detect a STOP in the middle of a read or a write */
+ if ((stat & DW_IC_INTR_STOP_DET) &&
+ (dev->status & (STATUS_READ_IN_PROGRESS | STATUS_WRITE_IN_PROGRESS))) {
+ dev_err(dev->dev, "spurious STOP detected\n");
+ dev->rx_outstanding = 0;
+ dev->msg_err = -EIO;
+ }
+
/*
* No need to modify or disable the interrupt mask here.
* i2c_dw_xfer_msg() will take care of it according to
@@ -834,6 +842,16 @@ i2c_dw_msg_is_valid(struct dw_i2c_dev *dev, const struct i2c_msg *msgs, size_t i
return false;
}

+ /*
+ * Make sure we don't need explicit RESTART between two messages
+ * in the same direction for controllers that cannot emit them.
+ */
+ if (!dev->emptyfifo_hold_master &&
+ (msgs[idx - 1].flags & I2C_M_RD) == (msgs[idx].flags & I2C_M_RD)) {
+ dev_err(dev->dev, "cannot emit RESTART\n");
+ return false;
+ }
+
return true;
}

diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 4e6fe3b55322..481a4eaaa28d 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -267,6 +267,7 @@ static void dw_i2c_plat_remove(struct platform_device *pdev)
}

static const struct of_device_id dw_i2c_of_match[] = {
+ { .compatible = "mobileye,eyeq6lplus-i2c" },
{ .compatible = "mscc,ocelot-i2c" },
{ .compatible = "snps,designware-i2c" },
{}

--
2.52.0