From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 31869259C80 for ; Wed, 6 May 2026 08:48:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778057308; cv=none; b=SGPOmdpYZPHwlDPpdjABvSEjwEPoGBCiHThfFwStgdC4GnVmczMc8U9PMvdAU9CrL4NeWeUOHKEeun4FbAAjEAJwHiap2eOXdfFgsPYrL9ZbH/n6cJIR5mxGsHys/0plvhC5pdahIqBfx15zZ2zEdf9foaM+WM/f80wzcwnajOE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778057308; c=relaxed/simple; bh=wrb8clZHgzuT7wnWp03Lc8ni6ePYR/XDW2BT0jrafHU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=hhzHVv8/a/nTgmt6C3bo6Q5g/JOBRaaTIGxab+m33wwOIfMMb4GJ/NibVs7FwCJVsh0BpyURlZgXhA5YDkboyM5BS6zu1XFMaljmwmjRlrGyl/8tk2k68bXbqcX4rETPTNDfmBV+V7zPRxXvbO7LJGoL0U9cvd6rIVldYeL9p2Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=FJsX3oJs; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="FJsX3oJs" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 252251A25; Wed, 6 May 2026 01:48:20 -0700 (PDT) Received: from localhost (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1D9C63F836; Wed, 6 May 2026 01:48:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778057305; bh=wrb8clZHgzuT7wnWp03Lc8ni6ePYR/XDW2BT0jrafHU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=FJsX3oJscwUJepHOsPZ3ynrLiBLn+T7I6Mc7PTjhGEj3JpgrdwU1lPyv0Ecn+R7K+ 4nHxkBhWl5vY3K/OeWMNLghyqCgDoBUcNDW9ZywX8pmQIfh/+wFcXiKGKyaX0Z2W2I 8WGNEfzptfk+txOWwvtvb0e8l4slKkWVzJ+hDl0o= Date: Wed, 6 May 2026 09:48:22 +0100 From: Leo Yan To: Yeoreum Yun Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, jie.gan@oss.qualcomm.com Subject: Re: [PATCH v6 04/13] coresight: etm4x: exclude ss_status from drvdata->config Message-ID: <20260506084822.GC3778514@e132581.arm.com> References: <20260422132203.977549-1-yeoreum.yun@arm.com> <20260422132203.977549-5-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260422132203.977549-5-yeoreum.yun@arm.com> On Wed, Apr 22, 2026 at 02:21:54PM +0100, Yeoreum Yun wrote: [...] > @@ -573,11 +573,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); > > for (i = 0; i < caps->nr_ss_cmp; i++) { > - /* always clear status bit on restart if using single-shot */ > - if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) > - config->ss_status[i] &= ~TRCSSCSRn_STATUS; > etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); > - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); > + /* always clear status and pending bits on restart if using single-shot */ > + etm4x_relaxed_write32(csa, 0x0, TRCSSCSRn(i)); I am not confident what is the right way to handle the pending bit. I looked a bit Arm ARM but still no clue. In particular, I suspect it may need to be handled when disabling the trace in etm4_disable_hw(). Let's make it clear with some internal check. > @@ -1829,8 +1829,8 @@ static ssize_t sshot_ctrl_store(struct device *dev, > raw_spin_lock(&drvdata->spinlock); > idx = config->ss_idx; > config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val); > - /* must clear bit 31 in related status register on programming */ > - config->ss_status[idx] &= ~TRCSSCSRn_STATUS; > + /* must clear bit 31 and 30 in related status register on programming */ > + drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING); Similarly, the question is: if it is in a pending state, how can we ensure the state machine works properly with the new settings? > raw_spin_unlock(&drvdata->spinlock); > return size; > } > @@ -1879,8 +1879,8 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, > raw_spin_lock(&drvdata->spinlock); > idx = config->ss_idx; > config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val); > - /* must clear bit 31 in related status register on programming */ > - config->ss_status[idx] &= ~TRCSSCSRn_STATUS; > + /* must clear bit 31 and 30 in related status register on programming */ > + drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING); Ditto. Thanks, Leo