From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E82CE4A2E20 for ; Wed, 6 May 2026 17:12:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778087538; cv=none; b=VXGhQMnEO2AqCJdLR3d8VatQ6zYJVBUIB1R0mpsNbGPdxFNBgcCBndtFEFgATRhIjGylTEnt5bza1AKSja1TrByKKoDysOGfKnYk9jWMF1fNo2uSxcGRTdKsrsx0lcyb82VhAhXeJKqsCMWnj5sTLrn8r+Xqf5s+1Xg+Z29gTQc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778087538; c=relaxed/simple; bh=2hNUxVHoGQuAyR29YQQH7T1ZGbZMsDe74AtxBXYr/aA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=je8+qw22XHXVqnN57eF71JIKpFOgjDf9rzE2TnBu1wc9NbcR/VWfdhkkSfNn3F+D0EynjQjC6lQYtCMrlT+3I5wfHBNNghm6nQRu3BS0/kACzEhdio4MA1GNn7XZqmLeBHXLI8aAyHRk+bTonVGgoM8tIHJirOYolSBm3TWcozg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=pU3H+fwr; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=bYaiM4mq; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="pU3H+fwr"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="bYaiM4mq" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 646A01H71985707 for ; Wed, 6 May 2026 17:12:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=w1cRVvCAgYq amAYxnwfv8V2B5dE0RzHQV0AEGiJrHmA=; b=pU3H+fwrJj/M+a/Pn4IGqg6Ifqw 05LPtYvhCmiaC2T4nIX09P4DLQFJkW0FUGIPcyvOQu48f5gjT5SZg7ioyl49MRnJ z9ZD9hahU4y/nO+oNzb4BqNwR2lD1ECuGvB+ytZwVTdxpKKL1v65jm+ftYiz7LZf RuMp7Vvl2WADPOfnttaWY3T+xFC7fZ9eqj59JcXdUCZKGJNDsyH+X6RYo/VP4Ril FaYyWLnNOVoxUHhn2i+Kp7Ji62VSX6TCnEzjeZrpfQCMjGqzF7+mUbzPS8v1PKOl xKlOrF6Q+wkXcxZxHSNUp4GW1YkDVPTpMvFydIjDhP+kH1LBKtYDgkT2lFQ== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e03gp1km2-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 06 May 2026 17:12:07 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2b458add85aso60550915ad.2 for ; Wed, 06 May 2026 10:12:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1778087526; x=1778692326; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w1cRVvCAgYqamAYxnwfv8V2B5dE0RzHQV0AEGiJrHmA=; b=bYaiM4mqJeTI/DdsS7qi+m3rQ1VqOosJMgeA4s0CvdNtFJJN2ZxBT1Ho1LKWNBlM/2 bEENY3y6+e5ZfYQiz0uqNL1W704Z35hG2Yds4C7kMriSN1VgSgv+4hAeksmv2gEQd78z DqCWNi7uD2jUJ5/hOvYf5Ca2K+nF9pQM1DfeZ10ISWuh+edtKKosuger1v3a0ijNSbdD gPfFOnIMCncPXpXOwkPxVBd0l7ozCPOq8/JQf7zwy22XmRwyfDQK4tPwfGzvXZ7P2UT4 TWGQyaDdoRTaGXw7QA4QkGcrYry2jv6PiziiljhMLjRZuJOprJtqrrazXr6aHnxv00VE BOAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778087526; x=1778692326; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=w1cRVvCAgYqamAYxnwfv8V2B5dE0RzHQV0AEGiJrHmA=; b=CJko2911YZa1ZoGUfPnOsIqL031qcJYBbep5rvzzrOdrlg+oLumU0v74HpRlF5tr/z nAAZwu9ac+EmF4H67wJCInbvDxNLDxXrq73kuXLADSiuzYFtvNtQCeVdQnIde2ZnARE2 1ao1vHpeAO0ss9lID2kRn7GsUsj1z1SC5eQqLQV7kqXpXhrwJN8x2SXjyrf9xvFznMH9 BkIX58GXxaVYrnMszmTiJW+3oBBWmblWEYzuqQb8DC6Wi/fk18I80w3wJKjAaEwiVCOo fSX0Gf2kGBEdmgcTrcotfi2Lfc99s77UZaG00gO2tUbvhsiuM4YDxsvvDH/vgYhITepQ 6xKg== X-Forwarded-Encrypted: i=1; AFNElJ9PKlpGTb0cjE3UgEp28kkuBxhiW0QTA3wvgvah3OlSmH9+r91mg6BVBfHCOE2pl+fAyIG9SRYrAPNtWmE=@vger.kernel.org X-Gm-Message-State: AOJu0Yw+azjCjPkg1syHTAdUjVLs5pK9wRqppgJZR9zl/gWkHrOsObyz eGHPWL/foIT01m62TJVvI8/YiYOy83bL/1BUwKz7xkHvlYIEMWWGFHBpYlpzpkCGTKvZOMwRssN XXeRZzmntVbQV+YuUzoippC4PKT8PJlrw8sgKSx7ZcSgEOkOYIFcg6KmWeTprpSsGQE8= X-Gm-Gg: AeBDies7TeJe3JUk0r+iMtmkXUQE5TvpOZ+Pw96Q5SFU8iS854PXDgjqUm6/PHJzfrf LId+5emp9+TpKBSlORn2j6q7Ry+T4oouVUaLQpfxHSx8R1zDhmXZdGoRjiytOq3OVDmjRtc0pmv jOa6lZBoM782EkDvw9HwSsii6t/D3OLtlTuW/qEzirDTj4yuIWTWyHpXHmc8xSgwNCGNtnFpEUj LpQM/mFgpXFY9oH/tT2Xkj9pVWAeHwfKuvWkCrmM6fPk4B/gB4qk+G6kMg0BeDE5exBlAF1Lhyz Acc3ORRBx6UqVjIA/cTAs9l5NDzNUQu/bxFqHjYBZQfXU6pzeyNOG6rpWYLjxH8b057o7S0B6WH /oS4lstifriZpPEUMhof7QtBsFwaidpNLiezQnRZ0hwQTbdllolHzZg== X-Received: by 2002:a05:6a20:918f:b0:3a1:2dbd:c30 with SMTP id adf61e73a8af0-3aa5ac8a6a8mr4437639637.45.1778087526167; Wed, 06 May 2026 10:12:06 -0700 (PDT) X-Received: by 2002:a05:6a20:918f:b0:3a1:2dbd:c30 with SMTP id adf61e73a8af0-3aa5ac8a6a8mr4437568637.45.1778087525586; Wed, 06 May 2026 10:12:05 -0700 (PDT) Received: from localhost ([2601:1c0:5000:d5c:4ec8:83f5:8254:6891]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c8242ad1317sm2844859a12.12.2026.05.06.10.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 10:12:05 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Akhil P Oommen , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 10/16] drm/msm: Add basic perfcntr infrastructure Date: Wed, 6 May 2026 10:10:34 -0700 Message-ID: <20260506171127.133572-11-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260506171127.133572-1-robin.clark@oss.qualcomm.com> References: <20260506171127.133572-1-robin.clark@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA2MDE2OCBTYWx0ZWRfX1bv9dipW51T9 JeRNr0Hr1WqVSL8gArR5wFuXn4cIo8K0cjZjvZkbICGMZ2uBUsDrSgwdV+NNi6pTcyY0hMizR3m Adme9broCa3DBwzkCbCoj7Wqh9s/vtVm28tQQox9HCI0A3TxIgXoyjOjlihDTrvf6Mx+Smfdmyb HRqFRm5UtKK43dfeeP318br/oh9QCBAciLq6YzMjDtGX0Ve0pUDdBh2nM/pKY1BVQ65Qsr9ulVn 5OsoqAXSOOp5EaMcTHSZiGBRbYeRf3s71/gPEwh1amsITOeputl/X0SAftg350fvMpxpO/coSw9 pqENKfMCOccZybhQ2eWkaT9IEZddg9vWBlUplza5Dx+VW7JTUUk0q2QvQVn4EeDVq1doZK5B+KS Oqrmat7XSy/Rs8sDIAIY/kyoSZIztyzI80xgfbxxKmGp7dMydN5/jn6kcPoL5RJ/Kl63yFWkScB bQoUWw1f5e0LXdwukWg== X-Proofpoint-ORIG-GUID: sIbNlZgF6S998ECMMVjYRGh0QBxqQ7QX X-Proofpoint-GUID: sIbNlZgF6S998ECMMVjYRGh0QBxqQ7QX X-Authority-Analysis: v=2.4 cv=W8wIkxWk c=1 sm=1 tr=0 ts=69fb7667 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=xqWC_Br6kY4A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=hddbS_E73Iye693R-v0A:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_01,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605060168 Add the basic infrastructure for tracking assigned perfcntrs. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/adreno_device.c | 8 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 +- drivers/gpu/drm/msm/msm_drv.h | 6 + drivers/gpu/drm/msm/msm_gpu.c | 12 ++ drivers/gpu/drm/msm/msm_gpu.h | 57 +++++++++- drivers/gpu/drm/msm/msm_perfcntr.c | 124 +++++++++++++++++++++ drivers/gpu/drm/msm/msm_perfcntr.h | 23 ++++ 8 files changed, 230 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/msm/msm_perfcntr.c diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 337634e7e247..2466cb32dac5 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -122,6 +122,7 @@ msm-y += \ msm_gpu_devfreq.o \ msm_io_utils.o \ msm_iommu.o \ + msm_perfcntr.o \ msm_rd.o \ msm_ringbuffer.o \ msm_submitqueue.o \ diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index fc38331ce640..7f20320ef66a 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -307,8 +307,10 @@ MODULE_DEVICE_TABLE(of, dt_match); static int adreno_runtime_resume(struct device *dev) { struct msm_gpu *gpu = dev_to_gpu(dev); - - return gpu->funcs->pm_resume(gpu); + int ret = gpu->funcs->pm_resume(gpu); + if (!ret) + ret = msm_perfcntr_resume(gpu); + return ret; } static int adreno_runtime_suspend(struct device *dev) @@ -322,6 +324,8 @@ static int adreno_runtime_suspend(struct device *dev) */ WARN_ON_ONCE(gpu->active_submits); + msm_perfcntr_suspend(gpu); + return gpu->funcs->pm_suspend(gpu); } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 72b71e9e44f0..ee0bcf985934 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -702,11 +702,10 @@ void adreno_recover(struct msm_gpu *gpu) struct drm_device *dev = gpu->dev; int ret; - // XXX pm-runtime?? we *need* the device to be off after this - // so maybe continuing to call ->pm_suspend/resume() is better? - + msm_perfcntr_suspend(gpu); gpu->funcs->pm_suspend(gpu); gpu->funcs->pm_resume(gpu); + msm_perfcntr_resume(gpu); ret = msm_gpu_hw_init(gpu); if (ret) { diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index e53e4f220bed..f00b2e7aeb91 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -235,6 +235,12 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, int msm_ioctl_vm_bind(struct drm_device *dev, void *data, struct drm_file *file); +int msm_perfcntr_resume(struct msm_gpu *gpu); +void msm_perfcntr_suspend(struct msm_gpu *gpu); + +struct msm_perfcntr_state * msm_perfcntr_init(struct msm_gpu *gpu); +void msm_perfcntr_cleanup(struct msm_gpu *gpu); + #ifdef CONFIG_DEBUG_FS unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); #endif diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 1bac70473f80..bf6845e5719e 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -1028,6 +1028,17 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, refcount_set(&gpu->sysprof_active, 1); + mutex_init(&gpu->perfcntr_lock); + + if (gpu->num_perfcntr_groups > 0) { + gpu->perfcntrs = msm_perfcntr_init(gpu); + if (IS_ERR(gpu->perfcntrs)) { + ret = PTR_ERR(gpu->perfcntrs); + gpu->perfcntrs = NULL; + goto fail; + } + } + return 0; fail: @@ -1066,6 +1077,7 @@ void msm_gpu_cleanup(struct msm_gpu *gpu) } msm_devfreq_cleanup(gpu); + msm_perfcntr_cleanup(gpu); platform_set_drvdata(gpu->pdev, NULL); } diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 19484774f369..be922641a14f 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -25,6 +25,7 @@ struct msm_gem_vm_log_entry; struct msm_gpu_state; struct msm_context; struct msm_perfcntr_group; +struct msm_perfcntr_stream; struct msm_gpu_config { const char *ioname; @@ -93,6 +94,13 @@ struct msm_gpu_funcs { */ bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); void (*sysprof_setup)(struct msm_gpu *gpu); + + /* Configure perfcntr SELect regs: */ + void (*perfcntr_configure)(struct msm_gpu *gpu, struct msm_ringbuffer *ring, + const struct msm_perfcntr_stream *stream); + + /* Flush perfcntrs before reading (optional): */ + void (*perfcntr_flush)(struct msm_gpu *gpu); }; /* Additional state for iommu faults: */ @@ -266,6 +274,11 @@ struct msm_gpu { const struct msm_perfcntr_group *perfcntr_groups; unsigned num_perfcntr_groups; + + struct msm_perfcntr_state *perfcntrs; + + /** @perfcntr_lock: protects perfcntr related state */ + struct mutex perfcntr_lock; }; static inline struct msm_gpu *dev_to_gpu(struct device *dev) @@ -311,10 +324,52 @@ static inline bool msm_gpu_active(struct msm_gpu *gpu) return false; } +/** + * struct msm_perfcntr_group_state - Tracking for the currently allocated counter state + */ +struct msm_perfcntr_group_state { + /** + * @allocated_counters: + * + * allocated counters for global counter collection. The + * corresponding counters are allocated from highest to + * lowest, to minimize chance of conflict with old userspace + * allocating from lowest to highest. + */ + unsigned allocated_counters; + + /** + * @countables: + * + * The correspnding SELect reg values for the allocated counters + */ + uint32_t countables[]; +}; + +/** + * struct msm_perfcntr_state - overall global perfcntr state + */ +struct msm_perfcntr_state { + /** @stream: current global counter stream if active */ + struct msm_perfcntr_stream *stream; + + /** + * @groups: Global perfcntr stream group state. + * + * Conceptually this is part of msm_perfcntr_stream state, but is + * statically pre-allocated when the gpu is initialized to simplify + * error path cleanup in PERFCNTR_CONFIG ioctl. (__free(kfree) + * doesn't really help with variable length arrays of allocated + * pointers.) + */ + struct msm_perfcntr_group_state *groups[]; +}; + static inline bool msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu) { - return refcount_read(&gpu->sysprof_active) > 1; + return (refcount_read(&gpu->sysprof_active) > 1) || + (gpu->perfcntrs && READ_ONCE(gpu->perfcntrs->stream)); } static inline bool diff --git a/drivers/gpu/drm/msm/msm_perfcntr.c b/drivers/gpu/drm/msm/msm_perfcntr.c new file mode 100644 index 000000000000..dad98c96863c --- /dev/null +++ b/drivers/gpu/drm/msm/msm_perfcntr.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "msm_drv.h" +#include "msm_gpu.h" +#include "msm_perfcntr.h" + +static int +msm_perfcntr_resume_locked(struct msm_perfcntr_stream *stream) +{ + return 0; +} + +int +msm_perfcntr_resume(struct msm_gpu *gpu) +{ + if (!gpu->perfcntrs) + return 0; + guard(mutex)(&gpu->perfcntr_lock); + return msm_perfcntr_resume_locked(gpu->perfcntrs->stream); +} + +static void +msm_perfcntr_suspend_locked(struct msm_perfcntr_stream *stream) +{ +} + +void +msm_perfcntr_suspend(struct msm_gpu *gpu) +{ + if (!gpu->perfcntr_groups) + return; + guard(mutex)(&gpu->perfcntr_lock); + msm_perfcntr_suspend_locked(gpu->perfcntrs->stream); +} + +/** + * msm_perfcntr_group_idx - map idx of perfcntr group to group_idx + * @stream: The global perfcntr stream + * @n: The requested group_idx + * + * The PERFCNTR_CONFIG ioctl requested N counters/countables per perfcntr + * group, but the order of groups is not required to match the order they + * are defined in the perfcntr tables (which is not stable/UABI, only the + * group names are UABI). + * + * But the order samples are returned in the stream should match the + * order they are requested in the PERFCNTR_CONFIG ioctl. This helper + * handles the order remapping. + * + * Returns an index into gpu->perfcntr_groups[] and perfcntrs->groups[]. + */ +uint32_t +msm_perfcntr_group_idx(const struct msm_perfcntr_stream *stream, uint32_t n) +{ + WARN_ON_ONCE(n > stream->nr_groups); + return stream->group_idx[n]; +} + +/** + * msm_perfcntr_counter_base - get idx of the first counter in group + * @stream: The global perfcntr stream + * @group_idx: the index of the counter group + * + * For global counter collection, counters are allocated from the end + * (last counter) to minimize the chance of conflict with an old UMD + * which predates PERFCNTR_CONFIG ioctl (since UMD assigned from 0..N-1). + * + * Returns the index of first counter to use. An index into + * msm_perfcntr_group::counters[]. + */ +uint32_t +msm_perfcntr_counter_base(const struct msm_perfcntr_stream *stream, uint32_t group_idx) +{ + struct msm_gpu *gpu = stream->gpu; + struct msm_perfcntr_state *perfcntrs = gpu->perfcntrs; + unsigned num_counters = gpu->perfcntr_groups[group_idx].num_counters; + unsigned allocated_counters = perfcntrs->groups[group_idx]->allocated_counters; + + return num_counters - allocated_counters; +} + +struct msm_perfcntr_state * +msm_perfcntr_init(struct msm_gpu *gpu) +{ + struct msm_perfcntr_state *perfcntrs; + struct device *dev = &gpu->pdev->dev; + size_t sz; + + sz = struct_size(perfcntrs, groups, gpu->num_perfcntr_groups); + perfcntrs = devm_kzalloc(dev, sz, GFP_KERNEL); + if (!perfcntrs) + return ERR_PTR(-ENOMEM); + + for (unsigned i = 0; i < gpu->num_perfcntr_groups; i++) { + const struct msm_perfcntr_group *group = + &gpu->perfcntr_groups[i]; + + sz = struct_size(perfcntrs->groups[i], countables, group->num_counters); + perfcntrs->groups[i] = devm_kzalloc(dev, sz, GFP_KERNEL); + if (!perfcntrs->groups[i]) { + msm_perfcntr_cleanup(gpu); + return ERR_PTR(-ENOMEM); + } + } + + return perfcntrs; +} + +void +msm_perfcntr_cleanup(struct msm_gpu *gpu) +{ + struct msm_perfcntr_state *perfcntrs = gpu->perfcntrs; + struct device *dev = &gpu->pdev->dev; + + gpu->perfcntrs = NULL; + + for (unsigned i = 0; i < gpu->num_perfcntr_groups; i++) + devm_kfree(dev, perfcntrs->groups[i]); + + devm_kfree(dev, perfcntrs); +} diff --git a/drivers/gpu/drm/msm/msm_perfcntr.h b/drivers/gpu/drm/msm/msm_perfcntr.h index 7f0654182496..bfda19e01535 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.h +++ b/drivers/gpu/drm/msm/msm_perfcntr.h @@ -35,6 +35,29 @@ struct msm_perfcntr_group { const struct msm_perfcntr_counter *counters; }; +/** + * struct msm_perfcntr_stream - state for a single open stream fd + */ +struct msm_perfcntr_stream { + /** @gpu: Back-link to the GPU */ + struct msm_gpu *gpu; + + /** @nr_groups: # of counter groups with enabled counters */ + uint32_t nr_groups; + + /** + * @group_idx: array of nr_groups + * + * Maps the order of groups in PERFCNTR_CONFIG ioctl to group idx, + * so that results in the results stream can be ordered to match + * the ioctl call that setup the stream + */ + uint32_t *group_idx; +}; + +uint32_t msm_perfcntr_group_idx(const struct msm_perfcntr_stream *stream, uint32_t n); +uint32_t msm_perfcntr_counter_base(const struct msm_perfcntr_stream *stream, uint32_t group_idx); + /** * struct msm_perfcntr_context_state - per-msm_context counter state * -- 2.54.0