From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF9434A2E3A for ; Wed, 6 May 2026 17:12:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778087549; cv=none; b=F3D3XbXaaaNvxTHK/v3aWDSSo1c+TlkXSgT19U2n/VqxMoG2GOpKRto7ZTxn0VhWbcohFBB+bukl3fOvF77wyLZm2J4OAx/oyzkv8KdGe+vzAoICP8bXjQA6H24weksrOpW7JoXvXNPR5WiDYcIIb4n/ueYA1db/mILnr0We2uM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778087549; c=relaxed/simple; bh=nSimtzMCf03reIDW/ZPwUxMG3evkLnwMtQ7AanDREFk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q2URWHhe/lFNvc+roqjbF8cYebPUGU+PHvzyFmlGgrwu6qcfwgIw0P5NHRoSWE6SqpXOzMJrKvB4jcMLa6Fn66ShjnbvQy1QMgd2+a9SXLAjY1pwV3eaPN7wRUxyOOlYGu+zubFY3UP2qEglPTWcMC0FQa475VuyLV2lK4B67J4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cwvoxX5K; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=AnlVOQR9; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cwvoxX5K"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="AnlVOQR9" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 646DeqOj1527943 for ; Wed, 6 May 2026 17:12:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=Ltx6YbZjqP0 n0TLXyDmoE2icoLsRZfk+xmP0o/mye+A=; b=cwvoxX5KO7zWLFEHNViksRIsoMf 0d1ZwErrxXaJyvgu7csZvX1XGcTS2GZoimbPPc9fMrJ+/3TF0dUauCy0yOXKqQoM z8PDRTZrt2/jtz7aTFwxqRUMb/Rw1YFFcoPnIkW68rG0MTOiwSpLtkHf3uRdFei+ ha6/rD1bCyekL6mwUKnVB2oiVExvFjOuUuwZsfOjo5u5+AGNl0UiZMGPmblMz7Gq lIZtdFjXvBWfW3IfVhGJcDOWnFsaHGnJv2hsC+C6ayJg4AhEYzRlMqYVIhSCrZtu ylEWNbc+O2jmbDdx6uNEn+0ab6804bvzDSfSvVHjEk7jiakWdFpdv62i+RA== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e0128ab0n-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 06 May 2026 17:12:17 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-82f74bcfb86so7052653b3a.0 for ; Wed, 06 May 2026 10:12:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1778087537; x=1778692337; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ltx6YbZjqP0n0TLXyDmoE2icoLsRZfk+xmP0o/mye+A=; b=AnlVOQR9DLW2h4GNP79uSKnDnLK9EBr111Wd61jrqgm/RXYCZIle0/pn7MxSrbOQAh Ebx/05K+aoS8lP668wfzxmLLmKa/XBP7LKSnZ8uQzJBp3GkEBBGlnRv/X5jRWEv7E7BG juhqdKOw4dNGbpfQs/3r7lZIkZS4eqlc1wlS/Bhs14I450twouR8A738z+aOJqxjqy2M Iyt5M9ZZI2D3nUIVNO9wVlVynA2NZwfkDFa6BlXDzcm0WJnGtXPIDXomD6Mxlr5Hup1f PtcKVmghcZJb6pbrKHl4xyOUWAwLCr/DkWRqFvoBaCcK0S3xMG+id3L1GPdhTslT4AwK IE9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778087537; x=1778692337; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Ltx6YbZjqP0n0TLXyDmoE2icoLsRZfk+xmP0o/mye+A=; b=Yhy9xUNkzyoESVS7SWWWR/QoMQ8SfBpzIg/fcjwbCI9t84kI2jy5Cn0W3WHKP0lFPa OZzuBZnB9FOXpgbpCSDHAWUpJoFgtw7HYAarxWIiKDb6vZrkc0mZrEZmSIC8CtCUc1nd Iule9P8lkVmRIPnBxx+uPe8STPbN8HFVSGs2U9gD5Ia1WJFeRaJSPkbPrDBvmTYRWPZY /Q6SCb5hU956wiwBPU7tbTTtSlNnaap8bsmAQQrMiORlVVZBVwiSv0Yyhe49ZmzMTps6 jp8cXbg89OgXWeDWq7w2NxHkY0su6Zj8cGOTznMznGKrf+CstdxbaSz3vJQc5UXZOuYB J8YA== X-Forwarded-Encrypted: i=1; AFNElJ+q1Xruw2Swj3MyvB6M+98bHQ3AX8yibF7PAaSBG4SJO+21kWvXUx3+752oV8DkkQ4wkCo2MAUJLUypZ48=@vger.kernel.org X-Gm-Message-State: AOJu0YzOWpc5RqK2LBvcqoLWEYXAsd/W6nxoKTsQ6nFdMSS0HTNbjM6M 46U7gBxcfubqmJhfKcIzK9TY6u4nCFQxCVE7cMFRuog0GJjnFmQA8erTMCq0jAEeXap8j05y2B1 RLqPQO3ObUB/GXjSQavXopo6VaL6S4fXj3YqJ3oUK275mapVrDD/+Q+hcdDrPKR4RpLE= X-Gm-Gg: AeBDieu52cTN1n60tRjBuUyYvbjDhukJj3qDGV8esfihjkEmdz1d8n1cZzE+bsFcgXV F2utFnW0sRUrWFuNc5kZYq5oHn+8VE0Bp90wF9cMgVkfShxX7P94SRvEmg78NIkwXeHf74ISqHh S6kBi4W8M4shj5K/sACndCXA1cC7OeKmWicJOrpUKZ36z0tXUQhKZQkJxFoOwAYZCvROU5djMkM qUORLFD2AiyZ0wGY20JyJtjC/gnsmWY2T2Npf2BTr8ccQ6nDRvcv0j3xTFYG0MHA7F6QKX9RmIS XSiYSXxBTkHoJhNagLxTh4QjC+nTbrFOD8RIBBLSP5Oe2s9GOD5BOXhdTtPseKRKCW2wHElTvDo 72dHXmVf2zhmxh1PWy/jJQQQIL6PMlXfk9IArJ6Takmd891EXA+BkQA== X-Received: by 2002:a05:6a00:2356:b0:81f:31c3:2e34 with SMTP id d2e1a72fcca58-83a5dd5c7a8mr4219517b3a.25.1778087536483; Wed, 06 May 2026 10:12:16 -0700 (PDT) X-Received: by 2002:a05:6a00:2356:b0:81f:31c3:2e34 with SMTP id d2e1a72fcca58-83a5dd5c7a8mr4219457b3a.25.1778087535860; Wed, 06 May 2026 10:12:15 -0700 (PDT) Received: from localhost ([2601:1c0:5000:d5c:4ec8:83f5:8254:6891]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-839682a4bffsm5597815b3a.56.2026.05.06.10.12.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 10:12:15 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 16/16] drm/msm/a6xx: Allow IFPC with perfcntr stream Date: Wed, 6 May 2026 10:10:40 -0700 Message-ID: <20260506171127.133572-17-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260506171127.133572-1-robin.clark@oss.qualcomm.com> References: <20260506171127.133572-1-robin.clark@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: uDfhnzJFPlTAIRZNUGh8qrUPgDXNKEPd X-Proofpoint-ORIG-GUID: uDfhnzJFPlTAIRZNUGh8qrUPgDXNKEPd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA2MDE2OCBTYWx0ZWRfX4U+L/oYg05e/ M4QYN8+IL5EJGSD+vbG6RC+jk3vJpAHFP0UdnyBNo8CnP1KLBraHo6IxOYGmOEjrOS2arf8PTlJ eaBe0a7tD7sXE8/B1iWg3JKnztypx2/3ni6ts7nrT1Jtj9hD1711WmlNHFr8AG2LDKL+xK30RJZ T1QsiMg9duOYgJiZJFA0hF1KLRc3Ks11RXKaqaYpOP1MkbHIUt9ic/DTbhEa35XQR06Ly8cQlDL WS1vL9s9RXLGu5HoKdMprGLrB4CE44qx0oslSVICqcpSPbfSkwsAq9p1gri7l3CPdAnflAgalBg GMA5UbaHSzmPj3bINN+2DIyxl0bdcBYKjPgIaPmsgIehmRdJk3P/FI6+frBRfJIghz/B3EP+BA5 prj5UeilyQH1hFWW/Pp63GQurJlVi+TftgmKEEgJmBCnBtKToaIcaX8XBBjmYY7+kaRKBq8Anuh 3J4F6hqWUJommMUMn0A== X-Authority-Analysis: v=2.4 cv=A8xc+aWG c=1 sm=1 tr=0 ts=69fb7671 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=xqWC_Br6kY4A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=5obZvuzjGUYrwyXX1KsA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_01,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 adultscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605060168 Now that the dynamic pwrup reglist has SEL reg values to restore appended, so that SEL regs are restored on IFPC exit, we can stop completely disabling IFPC while global counter sampling is active. To accomplish this, we re-use sysprof_setup() with a force_on param to inhibit IFPC specifically while the counter regs are being read, while leaving IFPC enabled the rest of the time. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 10 ++-------- drivers/gpu/drm/msm/msm_perfcntr.c | 8 ++++++++ drivers/gpu/drm/msm/msm_submitqueue.c | 2 +- 5 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index aba08fb76249..0a7d49a2c877 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2034,9 +2034,9 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, return irq; } -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu) +void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on) { - bool sysprof = msm_gpu_sysprof_no_ifpc(gpu); + bool sysprof = msm_gpu_sysprof_no_ifpc(gpu) || force_on; struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index f3cc9478b079..eecc71843bed 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -280,7 +280,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu); +void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on); void a6xx_preempt_init(struct msm_gpu *gpu); void a6xx_preempt_hw_init(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index cb74b7606987..e3b5fab6f68f 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -93,7 +93,7 @@ struct msm_gpu_funcs { * for cmdstream that is buffered in this FIFO upstream of the CP fw. */ bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); - void (*sysprof_setup)(struct msm_gpu *gpu); + void (*sysprof_setup)(struct msm_gpu *gpu, bool force_on); /* Configure perfcntr SELect regs: */ void (*perfcntr_configure)(struct msm_gpu *gpu, struct msm_ringbuffer *ring, @@ -378,13 +378,7 @@ msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu) static inline bool msm_gpu_sysprof_no_ifpc(struct msm_gpu *gpu) { - /* - * For now, this is the same condition as disabling perfcntr clears - * on context switch. But once kernel perfcntr IFPC support is in - * place, we will only need to disable IFPC for legacy userspace - * setting SYSPROF param. - */ - return msm_gpu_sysprof_no_perfcntr_zap(gpu); + return refcount_read(&gpu->sysprof_active) > 1; } /* diff --git a/drivers/gpu/drm/msm/msm_perfcntr.c b/drivers/gpu/drm/msm/msm_perfcntr.c index b7a9e3967a82..09e58a9a20bf 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.c +++ b/drivers/gpu/drm/msm/msm_perfcntr.c @@ -261,6 +261,10 @@ sample_worker(struct kthread_work *work) return; } + /* Inhibit IFPC while accessing registers: */ + if (gpu->funcs->sysprof_setup) + gpu->funcs->sysprof_setup(gpu, true); + if (gpu->funcs->perfcntr_flush) gpu->funcs->perfcntr_flush(gpu); @@ -295,6 +299,10 @@ sample_worker(struct kthread_work *work) } } + /* Re-enable IFPC: */ + if (gpu->funcs->sysprof_setup) + gpu->funcs->sysprof_setup(gpu, false); + smp_store_release(&stream->fifo.head, head); wake_up_all(&stream->poll_wq); } diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c index a58fe41602c6..1a5a77b28016 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -42,7 +42,7 @@ int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sy /* Some gpu families require additional setup for sysprof */ if (gpu->funcs->sysprof_setup) - gpu->funcs->sysprof_setup(gpu); + gpu->funcs->sysprof_setup(gpu, false); ctx->sysprof = sysprof; -- 2.54.0