From: Sean Christopherson <seanjc@google.com>
To: Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
Naveen N Rao <naveen@kernel.org>
Subject: [PATCH v2 0/5] KVM: SVM: Fix x2AVIC MSR interception issues
Date: Wed, 6 May 2026 11:47:41 -0700 [thread overview]
Message-ID: <20260506184746.2719880-1-seanjc@google.com> (raw)
Fix a variety of bugs in SVM's handling of x2APIC MSR passthrough for x2AVIC,
where KVM disables interception for MSR accesses that aren't accelerated by
hardware (pointless and suboptimal), and also does NOT disable interception
for practically any of the "range of vectors" MSRs, i.e. IRR, ISR, and TMR.
Found by inspection when reviewing a TDX patch to fix a bug where KVM botched
the "range of vectors"[*] (I was curious how other KVM code handled the ranges;
wasn't expecting this...).
Note, I tagged all of this for stable, but I could be convinced these fixes
shouldn't be sent to LTS trees. Patch 3 in particular doesn't truly fix
anything, though I definitely don't like relying on poorly documented behavior.
Note #2, the diff stats are misleading due to the hacks, the "real" stats are:
arch/x86/kvm/svm/avic.c | 51 ++++++++++++++++-----------------------------------
1 file changed, 16 insertions(+), 35 deletions(-)
[*] https://lore.kernel.org/all/20260318190111.1041924-1-dmaluka@chromium.org
v2:
- Actually iterate over the mask of readable regs. [Naveen]
- Rewrite the changelog for patch 3 to more accurately capture what happens,
and to avoid conflating "unaccelerated" with "fault-like". [Naveen]
- Massage the changlog for patch 1 to describe the observed behavior of
DFR and ICR2.
- Test the #VMEXIT (or not) behavior with hacks (patches 4 and 5).
v1: https://lore.kernel.org/all/20260409222449.2013847-1-seanjc@google.com
Sean Christopherson (5):
KVM: SVM: Disable x2AVIC RDMSR interception for MSRs KVM actually
supports
KVM: SVM: Always intercept RDMSR for TMCCT (current APIC timer count)
KVM: SVM: Only disable x2AVIC WRMSR interception for MSRs that are
accelerated
*** DO NOT MERGE *** KVM: x86: Hack in a stat to track guest-induced
exits (for testing)
*** DO NOT MERGE *** KVM: selftests: Add hacky test to verify x2APIC
MSR interception
arch/x86/include/asm/kvm_host.h | 2 +
arch/x86/kvm/svm/avic.c | 51 ++--
arch/x86/kvm/svm/svm.c | 81 +++++++
arch/x86/kvm/vmx/vmx.c | 79 +++++++
arch/x86/kvm/x86.c | 2 +
.../testing/selftests/kvm/include/x86/apic.h | 84 ++++++-
.../selftests/kvm/x86/fix_hypercall_test.c | 2 +-
.../selftests/kvm/x86/xapic_ipi_test.c | 4 +-
.../selftests/kvm/x86/xapic_state_test.c | 217 ++++++++++++++++++
9 files changed, 476 insertions(+), 46 deletions(-)
base-commit: 6d35786de28116ecf78797a62b84e6bf3c45aa5a
--
2.54.0.545.g6539524ca2-goog
next reply other threads:[~2026-05-06 18:47 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-06 18:47 Sean Christopherson [this message]
2026-05-06 18:47 ` [PATCH v2 1/5] KVM: SVM: Disable x2AVIC RDMSR interception for MSRs KVM actually supports Sean Christopherson
2026-05-06 18:47 ` [PATCH v2 2/5] KVM: SVM: Always intercept RDMSR for TMCCT (current APIC timer count) Sean Christopherson
2026-05-06 18:47 ` [PATCH v2 3/5] KVM: SVM: Only disable x2AVIC WRMSR interception for MSRs that are accelerated Sean Christopherson
2026-05-06 18:47 ` [PATCH v2 4/5] *** DO NOT MERGE *** KVM: x86: Hack in a stat to track guest-induced exits (for testing) Sean Christopherson
2026-05-06 18:47 ` [PATCH v2 5/5] *** DO NOT MERGE *** KVM: selftests: Add hacky test to verify x2APIC MSR interception Sean Christopherson
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