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Thu, 07 May 2026 01:07:38 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-365b0560fa8sm1986094a91.1.2026.05.07.01.07.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2026 01:07:38 -0700 (PDT) From: Mukesh Ojha To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Marko , Guru Das Srinagesh Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mukesh Ojha , Konrad Dybcio Subject: [PATCH 1/4] dt-bindings: firmware: qcom,scm: Add minidump SRAM property Date: Thu, 7 May 2026 13:37:17 +0530 Message-ID: <20260507080727.3227367-2-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260507080727.3227367-1-mukesh.ojha@oss.qualcomm.com> References: <20260507080727.3227367-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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Before DDR is initialised on the warm reset following a crash, firmware reads this word to decide if minidump is enabled and collect a minidump and where to deliver it (USB upload to a host, or save to local storage). Add 'sram' and 'sram-names' properties to the SCM binding to describe a region in always-on SRAM where the minidump download destination value could be written. Boot firmware reads it before DDR is initialised on a warm reset to decide where to store the minidump either to host PC or to on device storage. Most of the Qualcomm SoC supporting minidump supports this, added the kaanapali SoC for now. Suggested-by: Konrad Dybcio Signed-off-by: Mukesh Ojha --- .../bindings/firmware/qcom,scm.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 7918d31f58b4..6813081fd74a 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -127,6 +127,22 @@ properties: - description: offset of the download mode control register description: TCSR hardware block + sram: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Phandle to a region in always-on SRAM used to store the download + mode value for boot firmware to read before DDR is initialised on + the next warm reset. + maxItems: 1 + + sram-names: + items: + - const: minidump + +dependencies: + sram: [ sram-names ] + sram-names: [ sram ] + allOf: # Clocks - if: @@ -229,6 +245,18 @@ allOf: properties: memory-region: false + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,scm-kaanapali + then: + properties: + sram: false + sram-names: false + required: - compatible @@ -247,3 +275,32 @@ examples: clock-names = "core", "bus", "iface"; }; }; + + - | + /* kaanapali — minidump SRAM */ + / { + #address-cells = <2>; + #size-cells = <2>; + + sram@14680000 { + compatible = "qcom,kaanapali-imem", "mmio-sram"; + reg = <0x0 0x14680000 0x0 0x1000>; + ranges = <0x0 0x0 0x14680000 0x1000>; + no-memory-wc; + #address-cells = <1>; + #size-cells = <1>; + + minidump_config: minidump-config@1c { + reg = <0x1c 0x4>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-kaanapali", "qcom,scm"; + sram = <&minidump_config>; + sram-names = "minidump"; + #reset-cells = <1>; + }; + }; + }; -- 2.53.0