From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out30-131.freemail.mail.aliyun.com (out30-131.freemail.mail.aliyun.com [115.124.30.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23EC719539F; Thu, 7 May 2026 11:37:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153841; cv=none; b=GL7zC+qBbx+gabnDnmD7sRPqFu29aCa1+iOH/3WssggG9KUOq+57OStX35bu5rxqAMNNWGY41VaUJtbz9qmJ5wojRXV5CaYJPEAA0iGWMUvdx8pNiVRxP4aKLRPJPLlbUOlGKYtJgzgKgNu3O4sAKvWOEB55GdGNtqTwT3U/9Wg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153841; c=relaxed/simple; bh=t85LW6cpp4slZIdvI389Dyz9FRcdOHaqr2UsCHIUy+s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NXD8c3dnsV9XsDsIPg/CIgrmv95/cxLgrouNl+dMLGrSSZCnXq8mgL+Ez44/tk7CzIwQUhjfNWQIfO5s5JWyaznKJLJDylES8wFeJwf66TOQSt9OKACQ3OfWeNatFl+O9gZED94ZOSMjqMMuotjDfR+q28q/WNAUgpv9Alrh+fM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=DvJJpxoZ; arc=none smtp.client-ip=115.124.30.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="DvJJpxoZ" DKIM-Signature:v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778153836; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=e4f5X+R7i8qSI7NXq8cp591M8sz5EYh7qAQjjFxZJsY=; b=DvJJpxoZq1uJsDuQ+OvDbX0JyWSrUJDekFQVqonvnHcoyVanfXsiHbPquSAJlZGb+Yuju8q8NBqIeJ6mLLS6IMZAiP8/kBhJo+dhu8OYvKMwynluPrGgGc6h0Exg1U4qNbY9Soh2BDY8YY/cjiQEup3XecHl2MaEvPWvujNlDG4= X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R111e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033045098064;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=24;SR=0;TI=SMTPD_---0X2UVF-c_1778153833; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2UVF-c_1778153833 cluster:ay36) by smtp.aliyun-inc.com; Thu, 07 May 2026 19:37:14 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [RFC PATCH v2 02/10] iommupt: Add RISC-V dirty tracking PTE ops Date: Thu, 7 May 2026 19:36:58 +0800 Message-Id: <20260507113706.11400-3-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> References: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Fangyu Yu Implement the three dirty-tracking hooks required by the generic page table framework for the RISC-V format: pt_entry_is_write_dirty(): Check the D bit (bit 7) in the PTE. pt_entry_make_write_clean(): Clear the D bit across the full contiguous range. pt_entry_make_write_dirty(): Atomically set D via try_cmpxchg64() on a single PTE. Signed-off-by: Fangyu Yu --- drivers/iommu/generic_pt/fmt/riscv.h | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h index 777887335696..866b922f7e13 100644 --- a/drivers/iommu/generic_pt/fmt/riscv.h +++ b/drivers/iommu/generic_pt/fmt/riscv.h @@ -222,6 +222,49 @@ static inline void riscvpt_attr_from_entry(const struct pt_state *pts, } #define pt_attr_from_entry riscvpt_attr_from_entry +/* + * Dirty tracking: RISC-V PTEs use D (bit 7) as the hardware dirty bit. + * When Svnapot 64K is active a leaf entry spans 16 consecutive PTEs; we + * must check / clear all of them so that no dirty indication is lost. + */ +static inline bool riscvpt_entry_is_write_dirty(const struct pt_state *pts) +{ + unsigned int num_contig_lg2 = riscvpt_entry_num_contig_lg2(pts); + const pt_riscv_entry_t *tablep = + pt_cur_table(pts, pt_riscv_entry_t) + + log2_set_mod(pts->index, 0, num_contig_lg2); + const pt_riscv_entry_t *end = tablep + log2_to_int(num_contig_lg2); + + for (; tablep != end; tablep++) + if (READ_ONCE(*tablep) & RISCVPT_D) + return true; + return false; +} +#define pt_entry_is_write_dirty riscvpt_entry_is_write_dirty + +static inline void riscvpt_entry_make_write_clean(struct pt_state *pts) +{ + unsigned int num_contig_lg2 = riscvpt_entry_num_contig_lg2(pts); + pt_riscv_entry_t *tablep = + pt_cur_table(pts, pt_riscv_entry_t) + + log2_set_mod(pts->index, 0, num_contig_lg2); + pt_riscv_entry_t *end = tablep + log2_to_int(num_contig_lg2); + + for (; tablep != end; tablep++) + WRITE_ONCE(*tablep, READ_ONCE(*tablep) & ~(pt_riscv_entry_t)RISCVPT_D); +} +#define pt_entry_make_write_clean riscvpt_entry_make_write_clean + +static inline bool riscvpt_entry_make_write_dirty(struct pt_state *pts) +{ + pt_riscv_entry_t *tablep = + pt_cur_table(pts, pt_riscv_entry_t) + pts->index; + pt_riscv_entry_t new = pts->entry | RISCVPT_D; + + return try_cmpxchg64(tablep, &pts->entry, new); +} +#define pt_entry_make_write_dirty riscvpt_entry_make_write_dirty + /* --- iommu */ #include #include -- 2.50.1