From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F3B33C061D for ; Fri, 8 May 2026 09:42:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778233331; cv=none; b=raHa+1RF38rWRUE1TuMP/G5F3ESLpdv/7OumaOOE++zRGf6KbB0mWQ7zLP4jvEm9hkN/RzyFmiQJbixXOtag7PyJr4aYKcIGGgJXpnV+FXfdWmzzFiqM1C0XBnsbCqEwCJN0cU3UNAzPsQXdEtHJIHaJov6Qw5BRnUu+GT+QbdU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778233331; c=relaxed/simple; bh=Ng7f/Ng6zPtl5KJt5T+b4Vt/9C+9LhrfLa105ysMhuc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Yd/A1DiZH/GGlN4tC1Yfs35Zb84DrfHM9EFmDjGwqVOKQzldTogJqdClVpSJzLVJQnhcw90kQQCTObYxfN8Y3rABnGUmCTWOitDlmkZ0No7/H6sr2OqaHDmdzXcGzIod6dS9RV1gPK7KLki4rAk6c37gZ6mvmrlnjc6qTJnhMJo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Jsp4ANK/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Jsp4ANK/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2EB2FC2BCF5; Fri, 8 May 2026 09:42:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778233331; bh=Ng7f/Ng6zPtl5KJt5T+b4Vt/9C+9LhrfLa105ysMhuc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Jsp4ANK/0x+B6gBX4y+5UXM1HHwizaYIwWoqtOptRcaUy2UFOqaJCHJOyuQsTi4w2 8KD2gB9QJ081fCa7c47peA3w9cAdmuID66Ggojr28n7evvoHl1zLemG06UXsVGe/3c 83BokTOrBo+tKn5sX4yfTVJQUJ0fDqWjw6Khl19wC3zpWTrsJzGDuPjp04wSeTBtek EYTH++feSE9G8VBM0Q8GkLASl4CUqMh/Cvb5329yMzi1LvL5iju9gXn150hPf+PR6e 0PerWgTosEHKgcLfdkJXAXa1AT47g3MJ6cFbiqB/Adhglx3ESqal1FMXvyAURrQNf1 2StIRKiWsGM6Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wLHij-00000000HJz-1MJW; Fri, 08 May 2026 09:42:09 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH v2 4/5] clocksource/drivers/arm_arch_timer: Expose a direct accessor for the virtual counter Date: Fri, 8 May 2026 10:42:02 +0100 Message-ID: <20260508094203.2913880-5-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260508094203.2913880-1-maz@kernel.org> References: <20260508094203.2913880-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false We allow access to the architected counter via arch_timer_read_counter(). However, this accessor can either be the virtual or the physical view of the counter, depending on how the kernel has been booted. At the same time, we have some architectural features (such as WFIT, WFET) that rely on the virtual counter, and nothing else. If implementations were perfect, we'd rely on reading CNTVCT_EL0, and be done with it. However, we have a bunch of broken implementations in the wild, which rely on preemption being disabled and other costly workarounds. In order to provide decent performance on non-broken HW while still supporting the legacy horrors, expose arch_timer_read_vcounter() as a new helper that hides this complexity. Obviously, this is simply a global alias of arch_counter_get_cntvct(). Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 2 ++ include/clocksource/arm_arch_timer.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index ee21804d6613c..6fcd9afad38c2 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -137,6 +137,8 @@ static notrace u64 arch_counter_get_cntvct(void) u64 (*arch_timer_read_counter)(void) __ro_after_init = arch_counter_get_cntvct; EXPORT_SYMBOL_GPL(arch_timer_read_counter); +u64 arch_timer_read_vcounter(void) __attribute__((alias("arch_counter_get_cntvct"))); + static u64 arch_counter_read(struct clocksource *cs) { return arch_timer_read_counter(); diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h index 2eda895f19f54..587314e584839 100644 --- a/include/clocksource/arm_arch_timer.h +++ b/include/clocksource/arm_arch_timer.h @@ -88,6 +88,7 @@ struct arch_timer_mem { extern u32 arch_timer_get_rate(void); extern u64 (*arch_timer_read_counter)(void); +extern u64 arch_timer_read_vcounter(void); extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void); extern bool arch_timer_evtstrm_available(void); -- 2.47.3