From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E7BBB3F20E2 for ; Fri, 8 May 2026 15:27:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778254067; cv=none; b=EdjzfekUt6MSExwXLBQZKPqDmSoM2N1O7AvSB0jEL3OpafCBvgp0YCm8ZQTR4iS0tfmPk9kLgK4X7OswfeVEWhNmcLewjUmdos6wGMzv2EVQn6+h2x0U+hb1vSxLArPpThbz9C570Amu8pJ6HRpISHL+MTzCXhGiZHDUF+EvoHE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778254067; c=relaxed/simple; bh=fA9luiM0hxDLT0kv5HtcUycaXbjAO4oEDYzCee4bUcs=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ENKcWqEjdsRrqCNWn7wYYmzrk/wuRsgdowrxNIyWByPq7Th01eyJZ6KzDaDdzpr8PLgLJQ4e4w1SWGhe3EOxG+HJuL5kXFB3GNLRTSSG6FvsrBOOPbqprJszGMMTRsi5apZGMSozzGmsC0yyR8o0+nH98l5ZglwNCg4kNxPF+V0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=dv5caBrg; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="dv5caBrg" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D49BA3595; Fri, 8 May 2026 08:27:39 -0700 (PDT) Received: from localhost (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C78343F836; Fri, 8 May 2026 08:27:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778254065; bh=fA9luiM0hxDLT0kv5HtcUycaXbjAO4oEDYzCee4bUcs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=dv5caBrgjyIubJ/j5OmhQq1Gvro3YCti6XPY6zkK0iA3hkhnHpjFHFuXXZCQC/rLz rL/gS3JFe0CvkxVGzKzXCI8msOV0FPU5nwf0oL5fbiYioBJO0zppvwhfWj4XwGdDXZ kWoHqqLfw0LhiNFvVcFwltOzkmTlQrTreKceg5l4= Date: Fri, 8 May 2026 16:27:42 +0100 From: Leo Yan To: Yeoreum Yun Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, jie.gan@oss.qualcomm.com Subject: Re: [PATCH v6 04/13] coresight: etm4x: exclude ss_status from drvdata->config Message-ID: <20260508152742.GI3778514@e132581.arm.com> References: <20260422132203.977549-1-yeoreum.yun@arm.com> <20260422132203.977549-5-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260422132203.977549-5-yeoreum.yun@arm.com> On Wed, Apr 22, 2026 at 02:21:54PM +0100, Yeoreum Yun wrote: [...] > @@ -573,11 +573,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); > > for (i = 0; i < caps->nr_ss_cmp; i++) { > - /* always clear status bit on restart if using single-shot */ > - if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) > - config->ss_status[i] &= ~TRCSSCSRn_STATUS; > etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); > - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); > + /* always clear status and pending bits on restart if using single-shot */ > + etm4x_relaxed_write32(csa, 0x0, TRCSSCSRn(i)); After confirmed with hardware team, we should preserve status bits (including STATUS and PENDING bits) during a session. So here we should set drvdata->ss_status to TRCSSCSRn. > @@ -1503,8 +1501,9 @@ static void etm4_init_arch_data(void *info) > */ > caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); > for (i = 0; i < caps->nr_ss_cmp; i++) { > - drvdata->config.ss_status[i] = > - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); > + drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i)); > + drvdata->ss_status[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV | > + TRCSSCSRn_DA | TRCSSCSRn_INST); It is fine for read these capacity bits when probe, but we need to clear status when a session is starting to avoid the stale value left from previous session: drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING); We can do this in etm4_parse_event_config() for perf mode, and might create a new function (say etm4_parse_sysfs_config()) for preparing config for sysfs mode? The rest looks good to me. Thanks, Leo