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From: Chen Yu <yu.c.chen@intel.com>
To: kprateek.nayak@amd.com, tim.c.chen@linux.intel.com, peterz@infradead.org
Cc: pan.deng@intel.com, mingo@kernel.org,
	linux-kernel@vger.kernel.org, tianyou.li@intel.com
Subject: Re: [PATCH v2 1/4] sched/rt: Optimize cpupri_vec layout to mitigate cache line contention
Date: Sun, 10 May 2026 23:59:16 +0800	[thread overview]
Message-ID: <20260510155920.2587431-1-yu.c.chen@intel.com> (raw)
In-Reply-To: <729726b9-c669-41e2-887d-bdf9da703034@amd.com>

On Fri, Apr 10, 2026 at 11:32:09AM +0530, K Prateek Nayak wrote:
> Hello Chenyu, Tim,
>
> On 4/10/2026 11:21 AM, Chen, Yu C wrote:
> >>> I think per-LLC mask (or, as Tim suggested, 64CPUs per cacheline) is
> >>> a good tradeoff between the speedup vs amount of loads required to
> >>> piece together the full cpumask. Thoughts?
> > 
> > Yes, making it per LLC should work well enough (for balancing) to
> > achieve optimal benefit. Let me run some similar tests to yours,plus
> > hackbench/schbench, to see what the results are.
> > BTW, on AMD systems, does the TILE domain always match the CCX where
> > L3 is shared? On Intel the DIE is not always mapped to a domain
> > where L3 is shared.
> 
> On AMD platforms that support the extended leaf 0x80000026, CCX is
> always mapped to L3 and matched the data on 0x8000001D cache property
> leaf for L3.
> 
> > >> I agree that per-LLC mask is a good compromise between minimizing loads
> > >> and offer good speed ups.  I think we should get the LLC APICID
> > >> mask from 0x4 leaf (L1, L2, L3) instead of inferring from 0x1f leaf (Tile, Die ...etc)
> > >> for Intel.  And the cache leaf I think is 0x8000_001D leaf for AMD.
> > >> Those are parsed in cacheinfo code and we can get it from there.
> > 
> > Yes, let me check how we can leverage the l3 id for that.
> 
> Ack! I think the cacheinfo is better for all this and is also compatible
> with older systems that may nit have the extend topology enumeration
> leaf. AMD only got it two generations ago and until that only cache
> property leaf was used for marking the LLC (CCX) boundary.

Sorry for the delay. Here are the changes that create sbm leafs based
on cacheinfo. This can be applied on top of Peter's original patches and
Prateek's search optimization. We have not tested it yet, but it aims
to provide an evaluation prototype that prepares for next steps:
nohz idle mask evaluation, converting cpupri_vec->cpumask to per-LLC
granularity, etc. We will start testing nohz mask(if no objection on
this prototype) and share the results later.

thanks,
Chenyu



       reply	other threads:[~2026-05-10 16:08 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <729726b9-c669-41e2-887d-bdf9da703034@amd.com>
2026-05-10 15:59 ` Chen Yu [this message]
2026-05-10 15:59   ` [PATCH 1/3] x86/sbm: Fix domain shift calculation and sbm_find_next_bit() Chen Yu
2026-05-10 15:59   ` [PATCH 2/3] lib/sbm: Use dynamically sized bitmap in sbm_leaf Chen Yu
2026-05-10 15:59   ` [PATCH 3/3] x86/sbm: Derive leaf granularity from LLC cacheinfo instead of topology domain Chen Yu
2026-05-11  7:48     ` K Prateek Nayak
2026-05-12  9:29       ` Chen, Yu C

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