From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09EFE39F172 for ; Mon, 11 May 2026 07:48:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778485702; cv=none; b=HzeWn3S70nrMf0T3UltxmESHmL3D1mkpk0D1KO2Rq0SU833k6FnWyCIHb1VFQGA32MdsvxQbrjiNdCtWeimQF8Eku0wT0MW9Iqi6R16eg3N56Ywx8Cnn6W3mpxwiGoK4xaL+KCoUzEvuY7KQhGMRxHAJBovLRBkT44Nd0jxihZk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778485702; c=relaxed/simple; bh=s11kfFQEfwmRPGys4vi9dNVvePO0MgLuNby1VOtRHEE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=trQx3zzGvt/Q7XXr85CePS6hgxboTku+DrZNhsQFHZwZwBJ8aFMgyt3FDMzv19PbnTn7g2MuaG1jW4fyuLmjXXgO1UhgXWEduDzh2xQp555fc06qdifI9d4npT/CSoMabsOjLWQ0pATB7iMRL4dwiRD/WlhynJGQf+HRfmX4gbo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CQ0nEDzu; arc=none smtp.client-ip=209.85.208.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CQ0nEDzu" Received: by mail-lj1-f172.google.com with SMTP id 38308e7fff4ca-39396f873adso45610761fa.3 for ; Mon, 11 May 2026 00:48:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778485689; x=1779090489; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FCRPXJuyMzLZkmX2SvGMR/caiVTF8zEmEw035VGaKNA=; b=CQ0nEDzurYYLCNllRYCk4O3JVGzf3HZWTd6g37jKmrD8Wg/msEkt3i7TFKEHuR3bX+ XVTF6lTNAOlCgaBw5dpxFYIR1ewVYamwHwOewYRnqfdSjDcpp3B1oEFRFkJG0jR1nltu T9uSk0nP8PUhounf6HLyDaHV/frx3mm0raeK4H5XleYkDd6QDJEGrXNgwFF/xF+lgpgv T18p2rehxa7J884Gc5sLlGOygmcRb8yZ2+C+GH5jElOV34kj2vfPDIg51paHZZQuw+gN qgNtjjPCf6rchqQRQXGes30zyN/icUl3ckyOaxuCW9f6U7EwYbQZZUAw/sA1w8C1HTFY jNYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778485689; x=1779090489; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=FCRPXJuyMzLZkmX2SvGMR/caiVTF8zEmEw035VGaKNA=; b=Q8gInE86RehYSjMPXfzqLACBdgIFGPDl0EVFhZ8FBj6kHmsYDtWL6zApbpZ2xmOWzc jy1nB8FtK+tNv8jSCCEyrug/swmQJwf+ZI1aVxOOqolRfVJc3P5ZU8RbetAJz/g7J8pb b70iuthl9d4NZ42qHkTBYh5IIuWt9N+RyUEuHG4nZqOtkQndSIG03sVN33B/8PeGLT5w xBK1H6VdKL9d8mGBI0Tv24cRPgyGrURUP9x+ol5mdFc6XRHP+KqvY1Spn4f27diEZS9Z xk6guS1cxbg+UtFTAW6oW9QmnkQB8LxIOUzvtY+rvbm5x9RChOb4wOFjpo/5sLNSXE3P +yCw== X-Forwarded-Encrypted: i=1; AFNElJ8wqKaP2tt39xUwtdyPlLlF24cMnrkQ1C1kYJPfaHr9A9ZLZ99EjoWV1gk5CU0eZ87sUbn7BXQur4Qf3GQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yz4oKX/1/VpJuR0Jz0xX6sMadOwvmmBMSxBXXawOy13TxMvScel S+h0blBV0/E70gsagEIatLxa5MD2X+EAaFVzQWrNlRKK0E1lljBlm7tN X-Gm-Gg: Acq92OE9J0iGtAeY9R6ViJ+lE2dVF7Y7SYYMsIci3ta5NUawX45YmEgMkgyjpgs50j9 mONzzZREFyVlVlxHAezkvHFmJhwBhE3Ob1joPgs8uaJcLvCFNmqHVjlVIcJ7Aygn2fFyCKWNxTd 4+qVCuBy3+fabblt/B/0VGOfv7pxn+zptSWjFHs5Gsb7EcMjuRWn/V6RzHIFp23at/X3XeFDOmU FuC0bigBUMuu1Eu+mJ/AFwrDmBvdYufDuQHGbOWNfqcQ1jg0PK6EUZ0Rq5zTG8+aiXnfTxva0xu +xtP0x/4DT9VBKV1+6PUOOf7nUL7PxoE+FUGxm0werU3/Mmado+hDIJ0wtetbJXWHi3uXaHN7qc PmnO2ZqI25LeJ0ZUfSLMp4O9Q1or2ATAHpfOp16Xo5SqdN9PeXqi8zsXTWyDrqRJ761M/5UUMiZ fOhQTvTidaYO8z X-Received: by 2002:a05:6512:15a6:b0:5a8:9135:126e with SMTP id 2adb3069b0e04-5a8913516d3mr6026981e87.36.1778485688619; Mon, 11 May 2026 00:48:08 -0700 (PDT) Received: from xeon ([188.163.112.56]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a8a955e096sm2386670e87.38.2026.05.11.00.48.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 00:48:08 -0700 (PDT) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel , Ion Agorria , =?UTF-8?q?Jonas=20Schw=C3=B6bel?= Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/5] gpu/drm: tegra: dsi: add support for Tegra20/Tegra30 Date: Mon, 11 May 2026 10:47:51 +0300 Message-ID: <20260511074752.24745-5-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260511074752.24745-1-clamor95@gmail.com> References: <20260511074752.24745-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Tegra20/Tegra30 are fully compatible with existing tegra DSI driver apart clock configuration and MIPI calibration which are addressed by this patch. Signed-off-by: Svyatoslav Ryhel --- drivers/gpu/drm/tegra/drm.c | 2 ++ drivers/gpu/drm/tegra/dsi.c | 69 ++++++++++++++++++++++--------------- drivers/gpu/drm/tegra/dsi.h | 10 ++++++ 3 files changed, 54 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 4596073fe28f..5d64cd57e764 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -1359,10 +1359,12 @@ static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend, static const struct of_device_id host1x_drm_subdevs[] = { { .compatible = "nvidia,tegra20-dc", }, + { .compatible = "nvidia,tegra20-dsi", }, { .compatible = "nvidia,tegra20-hdmi", }, { .compatible = "nvidia,tegra20-gr2d", }, { .compatible = "nvidia,tegra20-gr3d", }, { .compatible = "nvidia,tegra30-dc", }, + { .compatible = "nvidia,tegra30-dsi", }, { .compatible = "nvidia,tegra30-hdmi", }, { .compatible = "nvidia,tegra30-gr2d", }, { .compatible = "nvidia,tegra30-gr3d", }, diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index 3f91a24ebef2..85bcb8bee1ae 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -662,39 +662,48 @@ static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) { u32 value; - value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); + /* Tegra20/30 uses DSIv0 while Tegra114+ uses DSIv1 */ + if (of_device_is_compatible(dsi->dev->of_node, "nvidia,tegra20-dsi") || + of_device_is_compatible(dsi->dev->of_node, "nvidia,tegra30-dsi")) { + value = DSI_PAD_CONTROL_LPUPADJ(0x1) | DSI_PAD_CONTROL_LPDNADJ(0x1) | + DSI_PAD_CONTROL_PREEMP_EN(0x1) | DSI_PAD_CONTROL_SLEWDNADJ(0x6) | + DSI_PAD_CONTROL_SLEWUPADJ(0x6) | DSI_PAD_CONTROL_PDIO(0) | + DSI_PAD_CONTROL_PDIO_CLK(0) | DSI_PAD_CONTROL_PULLDN_ENAB(0); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); + } else { + /* + * XXX Is this still needed? The module reset is deasserted right + * before this function is called. + */ + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); + + value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); + + value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | + DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | + DSI_PAD_OUT_CLK(0x0); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); + + value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | + DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); + } return 0; } static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) { - u32 value; int err; - /* - * XXX Is this still needed? The module reset is deasserted right - * before this function is called. - */ - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); - /* start calibration */ tegra_dsi_pad_enable(dsi); - value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | - DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | - DSI_PAD_OUT_CLK(0x0); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); - - value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | - DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); - err = tegra_mipi_start_calibration(dsi->mipi); if (err < 0) return err; @@ -1615,7 +1624,7 @@ static int tegra_dsi_probe(struct platform_device *pdev) goto remove; } - dsi->clk_lp = devm_clk_get(&pdev->dev, "lp"); + dsi->clk_lp = devm_clk_get_optional(&pdev->dev, "lp"); if (IS_ERR(dsi->clk_lp)) { err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp), "cannot get low-power clock\n"); @@ -1636,10 +1645,14 @@ static int tegra_dsi_probe(struct platform_device *pdev) goto remove; } - err = tegra_dsi_setup_clocks(dsi); - if (err < 0) { - dev_err(&pdev->dev, "cannot setup clocks\n"); - goto remove; + /* Tegra20/Tegra30 do not use DSI parent muxing */ + if (!of_device_is_compatible(dsi->dev->of_node, "nvidia,tegra20-dsi") && + !of_device_is_compatible(dsi->dev->of_node, "nvidia,tegra30-dsi")) { + err = tegra_dsi_setup_clocks(dsi); + if (err < 0) { + dev_err(&pdev->dev, "cannot setup clocks\n"); + return err; + } } regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -1709,6 +1722,8 @@ static const struct of_device_id tegra_dsi_of_match[] = { { .compatible = "nvidia,tegra132-dsi", }, { .compatible = "nvidia,tegra124-dsi", }, { .compatible = "nvidia,tegra114-dsi", }, + { .compatible = "nvidia,tegra30-dsi", }, + { .compatible = "nvidia,tegra20-dsi", }, { }, }; MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); diff --git a/drivers/gpu/drm/tegra/dsi.h b/drivers/gpu/drm/tegra/dsi.h index f39594e65e97..d834ac0c47ab 100644 --- a/drivers/gpu/drm/tegra/dsi.h +++ b/drivers/gpu/drm/tegra/dsi.h @@ -95,6 +95,16 @@ #define DSI_TALLY_LRX(x) (((x) & 0xff) << 8) #define DSI_TALLY_HTX(x) (((x) & 0xff) << 0) #define DSI_PAD_CONTROL_0 0x4b +/* Tegra20/Tegra30 */ +#define DSI_PAD_CONTROL_PULLDN_ENAB(x) (((x) & 0x1) << 28) +#define DSI_PAD_CONTROL_SLEWUPADJ(x) (((x) & 0x7) << 24) +#define DSI_PAD_CONTROL_SLEWDNADJ(x) (((x) & 0x7) << 20) +#define DSI_PAD_CONTROL_PREEMP_EN(x) (((x) & 0x1) << 19) +#define DSI_PAD_CONTROL_PDIO_CLK(x) (((x) & 0x1) << 18) +#define DSI_PAD_CONTROL_PDIO(x) (((x) & 0x3) << 16) +#define DSI_PAD_CONTROL_LPUPADJ(x) (((x) & 0x3) << 14) +#define DSI_PAD_CONTROL_LPDNADJ(x) (((x) & 0x3) << 12) +/* Tegra114+ */ #define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) #define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) -- 2.48.1