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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965d36a12sm17694642b3a.27.2026.05.11.00.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 00:51:49 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH 0/2] drm/verisilicon: add Nuvoton MA35D1 DCUltra Lite support Date: Mon, 11 May 2026 15:51:40 +0800 Message-ID: <20260511075142.54752-1-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds support for the Verisilicon DCUltra Lite display controller as integrated in the Nuvoton MA35D1 SoC. The Verisilicon DC driver and its DT binding were originally written by Icenowy Zheng for the TH1520 SoC, which carries a DC8000 IP block. The present series builds on that foundation with gratitude to Icenowy for the original work. The DCUltra Lite is a previous generation of the DC8000 series. While the two IPs share a broadly similar register layout, a number of differences prevent the existing driver from working on the MA35D1 without modification: - No chip identity registers: the DCUltra Lite does not expose model/revision/customer_id hardware registers, so variant detection must come from platform data rather than register reads. - No CONFIG_EX commit path: the DC8000 staging registers (FB_CONFIG_EX, FB_TOP_LEFT, FB_BOTTOM_RIGHT, FB_BLEND_CONFIG, PANEL_CONFIG_EX) are absent; the DCUltra Lite uses enable and reset bits in FB_CONFIG (bit 0 / bit 4) for direct framebuffer updates. - No PANEL_START register: panel output begins when PANEL_CONFIG.RUNNING is set; the DC8000 multi-display sync start register at 0x1CCC does not exist. - Different IRQ registers: IRQ_STA at 0x147C / IRQ_EN at 0x1480, versus the DC8000's IRQ_ACK at 0x0010 / IRQ_EN at 0x0014. - Simpler clock/reset topology: two clocks ("core" bus gate and "pix0" pixel divider), no driver-managed resets. The DC8000 requires core/axi/ahb clocks and three reset lines. - Single display output: no per-output indexing is needed. - Smaller register space: max_register 0x2000 vs. DC8000's 0x2544. Patch 1 extends the verisilicon,dc DT binding to accommodate variants with flexible clock/reset counts and adds a new sub-schema for nuvoton,ma35d1-dcu. Patch 2 introduces the vs_dc_info platform data structure, selects the correct code paths based on the detected IP family, extends Kconfig for ARCH_MA35, and wires up the "nuvoton,ma35d1-dcu" OF compatible string. Both patches have been tested on Nuvoton MA35D1 hardware and are functioning correctly. Joey Lu (2): dt-bindings: display: verisilicon,dc: generalize for DCUltra Lite variant drm/verisilicon: add support for Nuvoton MA35D1 DCUltra Lite display controller .../bindings/display/nuvoton,ma35d1-dcu.yaml | 94 +++++++++++++ .../bindings/display/verisilicon,dc.yaml | 64 +++++---- drivers/gpu/drm/verisilicon/Kconfig | 2 +- drivers/gpu/drm/verisilicon/vs_bridge.c | 28 ++-- drivers/gpu/drm/verisilicon/vs_crtc.c | 13 +- drivers/gpu/drm/verisilicon/vs_dc.c | 129 ++++++++++++------ drivers/gpu/drm/verisilicon/vs_dc.h | 1 + drivers/gpu/drm/verisilicon/vs_drm.c | 16 ++- drivers/gpu/drm/verisilicon/vs_hwdb.c | 2 +- drivers/gpu/drm/verisilicon/vs_hwdb.h | 25 ++++ .../gpu/drm/verisilicon/vs_primary_plane.c | 43 +++--- .../drm/verisilicon/vs_primary_plane_regs.h | 2 + 12 files changed, 318 insertions(+), 101 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/nuvoton,ma35d1-dcu.yaml -- 2.43.0