From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE0343A4F35 for ; Mon, 11 May 2026 13:01:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778504493; cv=none; b=Gvewd2TlD5FGDAgPCO+uNyglo66KZE665MOsKOWkMgkhsMh8KI+ldX0rSS/i33Pnh/OY5wWAXBl09giF2Djnwy5E+I21gb3KNmcdHRqp2YKF0VL7oV8/gppCkJqGtKr/DRAqDbPHNBFrMKXrDKHaP2hAYKIVFu0N2Is0uKdYI74= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778504493; c=relaxed/simple; bh=54SiiwIiDu5jCiPVBfargkA8Cq4AMd5thtK2yJft994=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EV6eZ8AJMrPLah6NaNVWlOhIRZQFYBGPATrtH/Cm71Amcf77qtND4qEaB1rT+chX63pliJGKgWSTK9d0f6nHtmRiR6LuvrBudFDxTPbmkKDefyfAKfEmV9sAC/xLdLcBiX38n/2UilcSaFxDWpIrDf35jIAS2ajFFjd6YKTa3V4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Qb79K+31; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=HkicUPYN; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Qb79K+31"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="HkicUPYN" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64BBIVHE1344479 for ; Mon, 11 May 2026 13:01:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=OJPIWHLYmtY h2vRJzlQwHbA8ExzYkFh40ePWlyvRs1s=; b=Qb79K+31KB/Tr2YfwFhERDvwKQy +Xe2jobb5rKhUwSc/HLzhGk24P8BCM/5gYt2rMI4/hT2b10QGJyuiOs1S6iYJ66y 7k3+mfF1Re0TVSnPEoP8iLkpbVen3BNWr0S4FFGKEIno8rMsqFvLpDyKP593nGeZ XiJxCzofedJGRr2RFc33lBYPcMkTRfAxYjjmjdqTJctpXCIqo9qrEXzkjgmm81by cdriA6u6oqozBhBN2XlxEyP7XKO5vmbc3jirXqrwHCvGCR1rvZui6QLbCKFYpVzM u8N869kexHZfSzUdAtcwVsex5e6R9wEi9H/bktDN7cvmhUZbyRoV47oRbHQ== Received: from mail-pj1-f70.google.com (mail-pj1-f70.google.com [209.85.216.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e3e498af9-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 11 May 2026 13:01:28 +0000 (GMT) Received: by mail-pj1-f70.google.com with SMTP id 98e67ed59e1d1-365e70c39d0so5591054a91.0 for ; Mon, 11 May 2026 06:01:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1778504488; x=1779109288; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OJPIWHLYmtYh2vRJzlQwHbA8ExzYkFh40ePWlyvRs1s=; b=HkicUPYN6WTDYOVqsoH7Mz/e/jA2Y/30nN3CgTiERSRbAvG1UiUIChA+6uzTM3GR3w a2nrP2ttXdkNspa0PvrQzrYGHssTK+KutJdxf8AJaY9PxlTFPfayMgAaKvGHz0hyVrAu ptEhHF5D3eUuc+HQniFjqqR32IYWgD7fGWcgox10G6tFYXi7frcDaPUEnSgPI5th1Pkx OKVEANtMs35sH+n0EHf7gNymeKGKkbQGZp4PVSkwgqcvdmFqjx9wgTpUCEvICEItXh2R 3WwIz93UwJ7iH+wz+LmapBU8+AL1BPS1RQUMO3kOzdNN0m1xJNY3DIdAVGU/3BjgCorf ovBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778504488; x=1779109288; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=OJPIWHLYmtYh2vRJzlQwHbA8ExzYkFh40ePWlyvRs1s=; b=kzbOUcCO7Oh2bAf7eyqJQYF/7pTyiExM5UqFFn5ZPQdVn48UOvJmkSJEAyFCSLgzDg kVOOo+RBKNOhrAJqR09rgFC90rf6osTeGhiH+lbOxFzRZdiDvSKPstrFtyOlVJxOfmtV f2CriKL0C1xaPY0f2FJkkp6LUdQ+zA3WQyQi2QcfMacnLMf9Y2f8X8Ds+cCKXKbcrUIN XGWALXPyhnB+Dz5uNkNcWpB5/Ozs1w8F9SkffrDzLASwJhsrAU0YBAactwk+dJU4EWXO mjj72yOHjfgY0MK3PhowGxgf6LkH7DZrwxFYx6M3+BrjoKgyDzrh9X7xVQRskdsSARan Y51g== X-Forwarded-Encrypted: i=1; AFNElJ+S0aoUNrfLMYpdjDOr4hELpaWYwq9iIEbypbn4l2/yNwYRbfzPbTz7iEJ8CQHGumRhPRye8qh/BMxVZnY=@vger.kernel.org X-Gm-Message-State: AOJu0YytYubO39rDKr+H0dLy2UsJomtE0ZBNXuin2uOPpKgu1SQE47DO Eky9Vwe+JEbE7pB7W5WhBvqv82ZvL1SLThGfnLqjtUEZCWyp7JoSIuA+4GPuO6Ez7Xdr+wpeGR6 lYxoi+2tfnCaRPxJruxcWgY7zGn7oyyh+sxsgBsNQnfYQJ5l8cDX41o6doI0+WJTSSWw= X-Gm-Gg: Acq92OGn2TGG2yre0sxSkFrEeMmMTf78y8YXMk3/vhmP+9zyb9Xn3+4SQLo4EiBG/Nd r9tneaWZSxq5/X1+gkikLEripLTu8dOCKcppk4ZTfSJV8nhUc8Y59VOLrTBpDHEBxRTgv7t0Zt8 I54EFhkZtwHYvx1ax2Sz5b9Djt8xJ9/fSwueEzW2tSgCNJZxo4fLy5XoEzeuAFC12px4BZsr2n7 +FxCZIFCF6bJRogw5YbOkq+Ke/XAQA5aRsNAIVr+lyd/8MTa/CJ7Yt7Ffvaj8j9ehIbR6aCYmjX nsFg0Qvxhz5PvtXIjwMS0yC99A3fxQq9kHXObXx4RpF1fw36P04dDUWMiBCvuWHNYJwP3FQeZUu dxPDrlvrbq3DccYfr2XMXLPiltrFdb3mI X-Received: by 2002:a17:903:22c9:b0:2ba:b5a3:187b with SMTP id d9443c01a7336-2bab5a31e16mr224167305ad.23.1778504487374; Mon, 11 May 2026 06:01:27 -0700 (PDT) X-Received: by 2002:a17:903:22c9:b0:2ba:b5a3:187b with SMTP id d9443c01a7336-2bab5a31e16mr224166345ad.23.1778504486632; Mon, 11 May 2026 06:01:26 -0700 (PDT) Received: from localhost ([2601:1c0:5000:d5c:4ec8:83f5:8254:6891]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d40434sm107088755ad.29.2026.05.11.06.01.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 06:01:25 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 11/16] drm/msm/a6xx+: Add support to configure perfcntrs Date: Mon, 11 May 2026 05:59:24 -0700 Message-ID: <20260511130017.96867-12-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260511130017.96867-1-robin.clark@oss.qualcomm.com> References: <20260511130017.96867-1-robin.clark@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 7x-PjB2_NiIksZ4WJp2v14LHIPtRcWE_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTExMDE0NCBTYWx0ZWRfX+/Ku7goNIn0g nIUEKK/d/pBYoTTEFusyo2wHOQARjBcfGofUst2Y7OJrt6SQMha8hmsu4mGKcpLE2xMehvnGznb XgtmuvcLDIQtGA0EA/cWH46edlqC8/bL2ULduHwLgv5epRFOsueK0FCuPQTBta3G8GECnBi3pxP JA8/G5U7P/xRDbbqUHUcJpQYodoqEkat/6GyfkgseV+r2yaUMGCBc+H9lIWcY45eMSA6e2U9D+w TLLgW7YkXAmMexfY9sbNbUkypo/okmfHTE0vKXl3MXMEy7F/vZiXnivM2tMogZb1rUHGqoFA6+v x2QZv4QuD/fE1cqZROSfiTCx0LVe0nvEEC/pn5lqhyLpVVVng7VJbRaNhvsV6S5bmEWmgO90/D4 +BMJW673l46IKreHuXQCSRcWF8eNkG+pCcHFtt2c6I4KZCJDG31m8kauaYIQg3/sPVV4u9A0DrU nSQXDQtTIMpo0b6mUQQ== X-Proofpoint-ORIG-GUID: 7x-PjB2_NiIksZ4WJp2v14LHIPtRcWE_ X-Authority-Analysis: v=2.4 cv=Yr0/gYYX c=1 sm=1 tr=0 ts=6a01d328 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=xqWC_Br6kY4A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=oWecmCczN8450n14xlQA:9 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-11_03,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 priorityscore=1501 phishscore=0 spamscore=0 suspectscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605110144 Add support to configure counter SELect regs. In some cases the reg writes need to happen while the GPU is idle. And for a7xx+, in some cases SEL regs need to be configured from BV or BR aperture. The easiest way to deal with this is to configure from the RB. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 69 +++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_perfcntr.h | 3 ++ drivers/gpu/drm/msm/msm_ringbuffer.h | 2 + 3 files changed, 74 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 415902f6e5d7..30df9bfa9ef8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2535,6 +2535,71 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return progress; } +static void +a6xx_perfcntr_configure(struct msm_gpu *gpu, struct msm_ringbuffer *ring, + const struct msm_perfcntr_stream *stream) +{ + enum adreno_pipe pipe = PIPE_NONE; + + for (unsigned i = 0; i < stream->nr_groups; i++) { + unsigned group_idx = msm_perfcntr_group_idx(stream, i); + unsigned base = msm_perfcntr_counter_base(stream, group_idx); + + const struct msm_perfcntr_group *group = + &gpu->perfcntr_groups[group_idx]; + + struct msm_perfcntr_group_state *group_state = + gpu->perfcntrs->groups[group_idx]; + + if (group->pipe != pipe) { + pipe = group->pipe; + + OUT_PKT7(ring, CP_THREAD_CONTROL, 1); + + if (pipe == PIPE_BR) { + OUT_RING(ring, CP_SET_THREAD_BR); + } else if (pipe == PIPE_BV) { + OUT_RING(ring, CP_SET_THREAD_BV); + } else { + OUT_RING(ring, CP_SET_THREAD_BOTH); + } + } + + const struct msm_perfcntr_counter *counter = &group->counters[base]; + unsigned nr = group_state->allocated_counters; + OUT_PKT4(ring, counter->select_reg, nr); + for (unsigned c = 0; c < nr; c++) + OUT_RING(ring, group_state->countables[c]); + + for (unsigned s = 0; s < ARRAY_SIZE(counter->slice_select_regs); s++) { + if (!counter->slice_select_regs[s]) + break; + + OUT_PKT4(ring, counter->slice_select_regs[s], nr); + for (unsigned c = 0; c < nr; c++) + OUT_RING(ring, group_state->countables[c]); + } + } + + if (pipe != PIPE_NONE) { + OUT_PKT7(ring, CP_THREAD_CONTROL, 1); + OUT_RING(ring, CP_SET_THREAD_BOTH); + } + + OUT_PKT7(ring, CP_MEM_WRITE, 3); + OUT_RING(ring, lower_32_bits(rbmemptr(ring, perfcntr_fence))); + OUT_RING(ring, upper_32_bits(rbmemptr(ring, perfcntr_fence))); + OUT_RING(ring, stream->sel_fence); + + a6xx_flush_yield(gpu, ring); + + /* Check to see if we need to start preemption */ + if (adreno_is_a8xx(to_adreno_gpu(gpu))) + a8xx_preempt_trigger(gpu); + else + a6xx_preempt_trigger(gpu); +} + static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) { if (!info->speedbins) @@ -2753,6 +2818,7 @@ const struct adreno_gpu_funcs a6xx_gpu_funcs = { .get_rptr = a6xx_get_rptr, .progress = a6xx_progress, .sysprof_setup = a6xx_gmu_sysprof_setup, + .perfcntr_configure = a6xx_perfcntr_configure, }, .init = a6xx_gpu_init, .get_timestamp = a6xx_gmu_get_timestamp, @@ -2786,6 +2852,7 @@ const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = { .create_private_vm = a6xx_create_private_vm, .get_rptr = a6xx_get_rptr, .progress = a6xx_progress, + .perfcntr_configure = a6xx_perfcntr_configure, }, .init = a6xx_gpu_init, .get_timestamp = a6xx_get_timestamp, @@ -2822,6 +2889,7 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs = { .get_rptr = a6xx_get_rptr, .progress = a6xx_progress, .sysprof_setup = a6xx_gmu_sysprof_setup, + .perfcntr_configure = a6xx_perfcntr_configure, }, .init = a6xx_gpu_init, .get_timestamp = a6xx_gmu_get_timestamp, @@ -2852,6 +2920,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = { .get_rptr = a6xx_get_rptr, .progress = a8xx_progress, .sysprof_setup = a6xx_gmu_sysprof_setup, + .perfcntr_configure = a6xx_perfcntr_configure, }, .init = a6xx_gpu_init, .get_timestamp = a8xx_gmu_get_timestamp, diff --git a/drivers/gpu/drm/msm/msm_perfcntr.h b/drivers/gpu/drm/msm/msm_perfcntr.h index bfda19e01535..14506bc37d05 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.h +++ b/drivers/gpu/drm/msm/msm_perfcntr.h @@ -45,6 +45,9 @@ struct msm_perfcntr_stream { /** @nr_groups: # of counter groups with enabled counters */ uint32_t nr_groups; + /** @sel_fence: Fence for SEL reg programming */ + uint32_t sel_fence; + /** * @group_idx: array of nr_groups * diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h index d1e49f701c81..28ca8c9f7463 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -37,6 +37,8 @@ struct msm_rbmemptrs { volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT]; volatile u64 ttbr0; volatile u32 context_idr; + + volatile u32 perfcntr_fence; }; struct msm_cp_state { -- 2.54.0