From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F057B3C9898; Tue, 12 May 2026 15:44:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778600664; cv=none; b=qsTux7lo0/JsdAYxMznDdRTJnDqmhPTA7c3jk0P5LuZkxFh19cC4Ygh8mZm0nZl5ONNd3IkrswQAOV/sRZKO8SNYO1I/ECYUXQiZMo5mY5Sp1/Qde10a8v0Ngb3Wbv7rWJWrw2AMeXz6sPNFeXAWgFU94UQlLFyGTc00mir5YBE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778600664; c=relaxed/simple; bh=1iseWDcRf6EDPp88AY5mtnrMFZ7P423KfW/rfCuNG1w=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=n1N6uYR6CIeeAve68uNzzcNfR0rfdeWzsH3lLntvxmC6Z5QrzkF1DzO29MKQh+AW4RqH5EN6rudEZE6LWf0UEQXl1h3+pkCM8gNfO4ve1VkgwtpftWg/3YEcYAXk841OXE82V/GC86qNaN9rE//lozFF6TVBLqnPxynv3lW6KDI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=jHorsZA9; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="jHorsZA9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1778600662; x=1810136662; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1iseWDcRf6EDPp88AY5mtnrMFZ7P423KfW/rfCuNG1w=; b=jHorsZA9HqQXcTjSnakVXcStgD4AK7l81K0CutCa1VQBb+fOyGjwUvG1 ov9kJcMCYDd0UGOlNa3xGPZ4pVlj/0j8/pfSPXQfaNw/fLSaNLzb3rjSA ZrzXPhxBBgR0zlj3cIyhqMw4j7rRNe0AKWZnwthAV4u1O6AzihPWtkEiE G1ukIWqB+kMx9PvphZn8Ts1HyAXco30BR+5/+mBovj6o83d9VcPmGn6vs 2vZ6oc6/YFXzw1vg0DMRx+fHkA57fTBnbKQ2xLGaCgBus7vSv8ZtXuSyt jdqW19Q/fdYRD91PfQ+fuJrZPWAXEzRznNv6SpMjvSx4XFFX+izsTnOcz Q==; X-CSE-ConnectionGUID: 1LHL1LrlQSWeonkBZq/K0w== X-CSE-MsgGUID: UPnM6DQqQyWFoiffY2LRAA== X-IronPort-AV: E=Sophos;i="6.23,231,1770620400"; d="scan'208";a="65713131" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 12 May 2026 08:44:22 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 12 May 2026 08:44:21 -0700 Received: from che-ll-i71840.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 12 May 2026 08:44:19 -0700 From: Balakrishnan Sambath To: CC: , , , , Subject: [PATCH v2 12/15] media: microchip-isc: reset pipeline state on kernel AWB enable Date: Tue, 12 May 2026 21:13:36 +0530 Message-ID: <20260512154339.210444-13-balakrishnan.s@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260512154339.210444-1-balakrishnan.s@microchip.com> References: <20251009155251.102472-1-balamanikandan.gunasundar@microchip.com> <20260512154339.210444-1-balakrishnan.s@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain gamma_lut_override and cc_coeff[] persist across control writes. When kernel AWB is enabled after userspace has customized the gamma curve or color correction matrix, the stale settings produce incorrect color. Clear gamma_lut_override and reset cc_coeff[] to identity when V4L2_CID_AUTO_WHITE_BALANCE is set to 1. Signed-off-by: Balakrishnan Sambath --- .../platform/microchip/microchip-isc-base.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 3749f473c3c6..e6386f8852e5 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -1730,10 +1730,22 @@ static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl) =20 switch (ctrl->id) { case V4L2_CID_AUTO_WHITE_BALANCE: - if (ctrl->val =3D=3D 1) + if (ctrl->val =3D=3D 1) { ctrls->awb =3D ISC_WB_AUTO; - else + /* + * Reset gamma and CC to defaults when enabling kernel + * AWB so it starts with a clean pipeline. + */ + ctrls->gamma_lut_override =3D false; + memset(ctrls->cc_coeff, 0, sizeof(ctrls->cc_coeff)); + ctrls->cc_coeff[0] =3D 256; /* RR */ + ctrls->cc_coeff[4] =3D 256; /* GG */ + ctrls->cc_coeff[8] =3D 256; /* BB */ + memset(ctrls->cc_offset, 0, sizeof(ctrls->cc_offset)); + ctrls->cc_dirty =3D true; + } else { ctrls->awb =3D ISC_WB_NONE; + } =20 /* configure the controls with new values from v4l2 */ if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new) --=20 2.34.1