Re: [PATCH v3 1/2] dt-bindings: memory: renesas,rzg3e-xspi: Add RZ/T2H and RZ/N2H support

[Rob Herring <robh@kernel.org>]

On Tue, May 05, 2026 at 12:24:04PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Document xSPI controller found on the Renesas RZ/T2H and RZ/N2H SoCs.
> The xSPI IP on these SoCs is identical to that found on the RZ/G3E SoC.
> 
> The RZ/G3E HW manual (Rev.1.15) references bridge channel 1 and its
> bits, however the hardware actually supports only a single bridge
> channel (channel 0), matching the RZ/T2H design. The references to
> channel 1 and its configuration bits will be corrected in a future
> revision of the HW manual.
> 
> Update clock/reset constraints to handle the SoC differences.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3:
> - Used RZ/G3E comptiable as a fallback compatible for
>   RZ/T2H and RZ/N2H SoCs since the xSPI IP is identical.
> - Updated commit message to reflect that the xSPI IP is
>  identical between RZ/G3E, RZ/T2H, and RZ/N2H SoCs.
> - Dropped RB tag from Rob due to above changes.
> 
> v1->v2:
> - Add RB tag from Rob for the dt-bindings patch.
> ---
>  .../renesas,rzg3e-xspi.yaml                   | 56 +++++++++++++++----
>  1 file changed, 46 insertions(+), 10 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml
> index 7a84f5bb7284..e2633476bd54 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml
> @@ -30,6 +30,8 @@ properties:
>            - enum:
>                - renesas,r9a09g056-xspi  # RZ/V2N
>                - renesas,r9a09g057-xspi  # RZ/V2H(P)
> +              - renesas,r9a09g077-xspi  # RZ/T2H
> +              - renesas,r9a09g087-xspi  # RZ/N2H
>            - const: renesas,r9a09g047-xspi
>  
>    reg:
> @@ -53,28 +55,38 @@ properties:
>        - const: err_pulse
>  
>    clocks:
> -    items:
> -      - description: AHB clock
> -      - description: AXI clock
> -      - description: SPI clock
> -      - description: Double speed SPI clock
> +    oneOf:
> +      - items:
> +          - description: AHB clock
> +          - description: AXI clock
> +          - description: SPI clock
> +          - description: Double speed SPI clock
> +      - items:
> +          - description: AHB clock
> +          - description: SPI clock
>  
>    clock-names:
> -    items:
> -      - const: ahb
> -      - const: axi
> -      - const: spi
> -      - const: spix2
> +    oneOf:
> +      - items:
> +          - const: ahb
> +          - const: axi
> +          - const: spi
> +          - const: spix2
> +      - items:
> +          - const: ahb
> +          - const: spi
>  
>    power-domains:
>      maxItems: 1
>  
>    resets:
> +    minItems: 1
>      items:
>        - description: Hardware reset
>        - description: AXI reset
>  
>    reset-names:
> +    minItems: 1
>      items:
>        - const: hresetn
>        - const: aresetn
> @@ -109,6 +121,30 @@ required:
>    - '#address-cells'
>    - '#size-cells'
>  
> +if:
> +  properties:
> +    compatible:
> +      contains:
> +        enum:
> +          - renesas,r9a09g077-xspi
> +          - renesas,r9a09g087-xspi
> +then:
> +  properties:
> +    clocks:
> +      maxItems: 2
> +    clock-names:
> +      maxItems: 2

What about resets?:

resets:
  maxItems: 1


> +else:
> +  properties:
> +    clocks:
> +      minItems: 4
> +    clock-names:
> +      minItems: 4
> +    resets:
> +      minItems: 2
> +    reset-names:
> +      minItems: 2
> +
>  unevaluatedProperties: false
>  
>  examples:
> -- 
> 2.54.0
> 
>