From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE4353BFAE1 for ; Wed, 13 May 2026 21:35:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778708111; cv=none; b=Awbyt59qi0mA9XQwtMzLT3qxzBlL04eZmhfiVWTwYMWWFMXIMrvsdVJQeyAAlv3xos0M5kKT1ibrfgImm6nn9ST7Psn7Ez6EjRS8Ip+/emtnWNF0VIBsjqJb4xukLoL7XRwazy1kZhF2OsSvdVsmFvIZXc4r818HKIFfkOnwbTc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778708111; c=relaxed/simple; bh=fcg5dGJNBAQyU4b2cL0nA3wqgVJTqz/EfkeGsaL9qZo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HmodNhRP2SbZIVRT56jBclkY8pX07MekSLCfAPT55qd3l1OGOSoQPILx5w6ExNs31HRqH5+Hl0alJVSagpJLWg7Gw6ee2kOjL/8Lkt5G4xL67VFVVddsXM71cYLFGtHWq58/cQKR/ROB1oEhnBF46+EWPAi3CelCQb/S5YGXeQs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=QcSK/TOw; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QcSK/TOw" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-48374014a77so64091315e9.3 for ; Wed, 13 May 2026 14:35:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778708105; x=1779312905; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ilUL26n1rjGYeNrOGQ28D9s1uztNCB3AEwbB2W2pXWM=; b=QcSK/TOwj+vFz6gW3iV15mckfT4BSKXGaYPkctagMNZOyUhdUBkYiGvridRlCqtaZl OqZGtILhBadOgCFVTekt/G17rs/6yIIpaaNLVVcurJn8PMhcUuz0LN5zb+qkuZt+pszv 23kKjmBX3rG0eVaOTAdUFeUjUm0iiSgeho26usMO8RsEoNlPxKSF0wcRyQlJrvdyZPF+ mg8iP3GOTZ+pAHddoSCcZ7dPcS6axNyo/lmtMFZcvTUbAT4pY3pl2Bq17opeariXD1nE Va9kEDS1OIXMDZB9CqL8uhO8KXfawFlGjb/FLNei0oR+5QaLqywXq9T1rOuW4wlWLMva dNzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778708105; x=1779312905; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ilUL26n1rjGYeNrOGQ28D9s1uztNCB3AEwbB2W2pXWM=; b=PU8fTCVBAasv1FJtNZL5Bg4Gvnd1qPCFZpqBaO4l+1lRkY2CwXlAE07jtnw2LuXaOz JeoRwGhtwc2lu/KTnFquCFyP73co/NvRiAavqbPZ71zy4Ve3YshdjSp7IEKMiFmAx9bX HLpxgPTKy3offqrwrNlsD3IVab3cdIohD7Pp2XTX/MGNqIIbidcQ2ZcLQhZvauX/AJ20 KvP7jxnuaGuK8D5qIAfUKXwM8XF9uxptWAtnDfjpun23+YIYSd2fCPlWP4pZa+lYU5A8 j90ifLm/nPNXkD0CncenJhhB6tFqC0OO+WDuZOChgrt//yAhSytoN1MBQH7A4hO0YLY2 BIzg== X-Forwarded-Encrypted: i=1; AFNElJ+gdpd0gRJhd6lnhb1Be7/dBok4EyjuNhKiBwhDMnO2y42XpYaymAqR0jG6eUWNEjZ4U8yZDhasAQmnSsE=@vger.kernel.org X-Gm-Message-State: AOJu0YykbPX1li3cVZ52IFZ0RfMp8Np+Crr8TJBtmYNvwPB6E2pUX787 rqmvQpFDTbGuNEo+oB9btySHwYtT8bZG0EesK91w8Pl9wNtSn/wOgUo0AIpnfF2dGuY= X-Gm-Gg: Acq92OHS1j52SzA6otln7lbRqCd7WZfdAajTtwuCXN8tBKLBpfltbOZnarGchTaBQ/+ Jkues9zYerNtSxY2u/21hvaz2JGml5PeBxpPDb7aktx89CKTGlyJN7+Z+W6TNCETRfEan8wTEq9 d6LfnIK2TDJLVacjd59H2QokTAEPSORmxg3Ft/XW5vVoO4laIdeVmh3ne8JU5410jQpzQOlvIE3 Nc20scEoKuab/9e9qec0kg3xYSxJlKY7/iHixBRpDDPiDcJuPA5Fq05CcodUrhxyt5xK32Dvm1C Eua6AtHMDYOMo3+pVHlX4DaQtIMVQV4bofuAN3UGOC8R2Znr+dDcZHKwtbfHrYSnQZ6lxgR5M8u UaeWTGLXPAfhE03/EOCPQ4GD08Rg4KxAUawHP5IluYNgbfVxYdAqHkWH3cxiqCbAsChqXmwXrPo a7nVgrHfcVPMf/zX4QbbHnQv37vnXe+p2/rfjhMngtmwc= X-Received: by 2002:a05:600c:4fcb:b0:48e:5d91:cffb with SMTP id 5b1f17b1804b1-48fc9a0f637mr70497135e9.10.1778708104526; Wed, 13 May 2026 14:35:04 -0700 (PDT) Received: from [192.168.0.2] ([197.250.51.99]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fdb1fee9csm2553055e9.0.2026.05.13.14.35.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 14:35:04 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Thu, 14 May 2026 00:34:56 +0300 Subject: [PATCH 1/2] ARM: zte: Add support for zx29 low level debug Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260514-zx29uart-v1-1-68470ecc3977@gmail.com> References: <20260514-zx29uart-v1-0-68470ecc3977@gmail.com> In-Reply-To: <20260514-zx29uart-v1-0-68470ecc3977@gmail.com> To: Russell King , Greg Kroah-Hartman , Jiri Slaby Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, =?utf-8?q?Stefan_D=C3=B6singer?= , Linus Walleij X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2902; i=stefandoesinger@gmail.com; h=from:subject:message-id; bh=fcg5dGJNBAQyU4b2cL0nA3wqgVJTqz/EfkeGsaL9qZo=; b=owEBiQJ2/ZANAwAIAT0TvMhUTxoiAcsmYgBqBO6DHrxaXkARBemDDkrBXpRS3oDZcwST0k/6L QLZOUY6KB+JAk8EAAEIADkWIQRDFvS2qgVbJ5UyXWw9E7zIVE8aIgUCagTugxsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwyLDIACgkQPRO8yFRPGiJwjg//XTrdw6+H+63UW2tqzNvWFZC4aWlyYUj gjO5KfX3MtxNMlzZPWOaHkRmJ6iIfTMtSzw0HVwWP8qpWmyauwAyXiVkiSb/cYBR+zTDOCKh8ct 2O4/xKK/IxkSkqRJpZFZKUVxPHj96SwxDRx+XljqC2wPPlG2otentnHSTQBnME/vCXr21QqlX2d oMn/b3jzcNV5QL5RnBowJT0eG54v7ImmhvtP7D/NmVYP341gctaRixem8tVc5VNDcLZQCTUX6/Z jBZg7B5gOsBAe9367QIzSIYsIQ8mGWggHslNjUVnnCHF1wFVJBcfKFiGDa0davUavrGKwpmvLpf i93Rj1OnEPKMqp1LVXhgehpD4nXBFgXUSLaHSggtnRK5IdIfm9VHSX5VTGM/Gy4gSTxy70APCTX z0OpWcnd+RoFpWF0R2G7l07WtpRE/f1KdpogeWPz93/gK1+q9l5j6/1ar51/DFaS/ILJeQuokEV 3uoOf4WZF24/O3/nm3WcdjLRalLqAKvDj4UWFnHVoZ7juBtaOIaP+7NMAyVduI9WJ0GnCHyHUC9 tqjHKhEVWLebrkNuv4zFtLz5BmtgBbTyRhhGbMTJKIgdRDuMbNWq2Hy8XR7ZQpPXWwKx+VM2Jaj o1YS12nYo9yXnK3LtuDuvApaJ3Bb7g9H555OERinTF5PknMfisFk= X-Developer-Key: i=stefandoesinger@gmail.com; a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This is based on the removed zx29 code. A separate (more complicated) patch will re-add the register map to the pl011 serial driver. Reviewed-by: Linus Walleij Signed-off-by: Stefan Dösinger --- Patch changelog: v8: Adjust UART01x_FR_BUSY to match the different ZX UART registers (Sashiko). I am unsure about UART01x_FR_TXFF and my boards do not expose flow control pins to allow me to test if it works. I am unsure about the virtual address. It doesn't seem to matter, as long as it is a valid address. This address is based on the old removed code. Is there a rule-of-thumb physical to virtual mapping I can use to give a sensible default value? --- arch/arm/Kconfig.debug | 12 ++++++++++++ arch/arm/include/debug/pl01x.S | 9 +++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 366f162e147d..98d8a5a60048 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1331,6 +1331,16 @@ choice This option selects UART0 on VIA/Wondermedia System-on-a-chip devices, including VT8500, WM8505, WM8650 and WM8850. + config DEBUG_ZTE_ZX + bool "Kernel low-level debugging via zx29 UART" + select DEBUG_UART_PL01X + depends on ARCH_ZTE + help + Say Y here if you are enabling ZTE zx297520v3 SOC and need + debug UART support. This UART is a PL011 with different + register addresses. The UART for boot messages on zx29 boards + is usually UART1 and is operating at 921600 8N1. + config DEBUG_ZYNQ_UART0 bool "Kernel low-level debugging on Xilinx Zynq using UART0" depends on ARCH_ZYNQ @@ -1545,6 +1555,7 @@ config DEBUG_UART_8250 config DEBUG_UART_PHYS hex "Physical base address of debug UART" + default 0x01408000 if DEBUG_ZTE_ZX default 0x01c28000 if DEBUG_SUNXI_UART0 default 0x01c28400 if DEBUG_SUNXI_UART1 default 0x01d0c000 if DEBUG_DAVINCI_DA8XX_UART1 @@ -1701,6 +1712,7 @@ config DEBUG_UART_VIRT default 0xf31004c0 if DEBUG_MESON_UARTAO default 0xf4090000 if DEBUG_LPC32XX default 0xf4200000 if DEBUG_GEMINI + default 0xf4708000 if DEBUG_ZTE_ZX default 0xf6200000 if DEBUG_PXA_UART1 default 0xf7000000 if DEBUG_SUN9I_UART0 default 0xf7000000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0 diff --git a/arch/arm/include/debug/pl01x.S b/arch/arm/include/debug/pl01x.S index c7e02d0628bf..9dcdeed2357d 100644 --- a/arch/arm/include/debug/pl01x.S +++ b/arch/arm/include/debug/pl01x.S @@ -8,6 +8,15 @@ */ #include +#ifdef CONFIG_DEBUG_ZTE_ZX +#undef UART01x_DR +#undef UART01x_FR +#undef UART01x_FR_BUSY +#define UART01x_DR 0x04 +#define UART01x_FR 0x14 +#define UART01x_FR_BUSY (1<<8) +#endif + #ifdef CONFIG_DEBUG_UART_PHYS .macro addruart, rp, rv, tmp ldr \rp, =CONFIG_DEBUG_UART_PHYS -- 2.53.0