From: Krzysztof Kozlowski <krzk@kernel.org>
To: Jian Hu <jian.hu@amlogic.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Xianwei Zhao <xianwei.zhao@amlogic.com>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 03/10] dt-bindings: clock: Add Amlogic A9 peripherals clock controller
Date: Fri, 15 May 2026 10:10:37 +0200 [thread overview]
Message-ID: <20260515-augmented-cyber-puffin-4db20f@quoll> (raw)
In-Reply-To: <20260511-b4-a9_clk-v1-3-41cb4071b7c9@amlogic.com>
On Mon, May 11, 2026 at 08:47:25PM +0800, Jian Hu wrote:
> Add the peripherals clock controller dt-bindings for the Amlogic A9
> SoC family.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
> .../clock/amlogic,a9-peripherals-clkc.yaml | 150 +++++++++
> .../clock/amlogic,a9-peripherals-clkc.h | 352 +++++++++++++++++++++
> 2 files changed, 502 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml
> new file mode 100644
> index 000000000000..97e2c44d8630
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml
> @@ -0,0 +1,150 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2026 Amlogic, Inc. All rights reserved
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/amlogic,a9-peripherals-clkc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Amlogic A9 Series Peripherals Clock Controller
> +
> +maintainers:
> + - Neil Armstrong <neil.armstrong@linaro.org>
> + - Jerome Brunet <jbrunet@baylibre.com>
> + - Jian Hu <jian.hu@amlogic.com>
> + - Xianwei Zhao <xianwei.zhao@amlogic.com>
> +
> +properties:
> + compatible:
> + const: amlogic,a9-peripherals-clkc
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> + clocks:
> + minItems: 20
I don't think so. How they could be optional in silicon? How does
exactly work from silicon point of view?
> + items:
> + - description: input oscillator
> + - description: input fclk div 2
> + - description: input fclk div 3
> + - description: input fclk div 4
> + - description: input fclk div 5
> + - description: input fclk div 7
> + - description: input fclk div 2p5
> + - description: input sys clk
> + - description: input gp1 pll
> + - description: input gp2 pll
> + - description: input sys pll div 16
> + - description: input cpu clk div 16
> + - description: input a78 clk div 16
> + - description: input dsu clk div 16
> + - description: input rtc clk
> + - description: input gp0 pll
> + - description: input hifi0 pll
> + - description: input hifi1 pll
> + - description: input mclk0 pll
> + - description: input mclk1 pll
> + - description: input video1 pll (optional)
> + - description: input video2 pll (optional)
> + - description: input hdmi out2 clk (optional)
> + - description: input hdmi pixel clk (optional)
> + - description: input pixel0 pll (optional)
> + - description: input pixel1 pll (optional)
> + - description: input usb2 drd clk (optional)
> + - description: external input rmii oscillator (optional)
> +
> + clock-names:
> + minItems: 20
> + items:
> + - const: xtal
> + - const: fdiv2
> + - const: fdiv3
> + - const: fdiv4
> + - const: fdiv5
> + - const: fdiv7
> + - const: fdiv2p5
> + - const: sys
> + - const: gp1
> + - const: gp2
> + - const: sysplldiv16
> + - const: cpudiv16
> + - const: a78div16
> + - const: dsudiv16
> + - const: rtc
> + - const: gp0
> + - const: hifi0
> + - const: hifi1
> + - const: mclk0
> + - const: mclk1
> + - const: vid1
> + - const: vid2
> + - const: hdmiout2
> + - const: hdmipix
> + - const: pix0
> + - const: pix1
> + - const: u2drd
> + - const: ext_rmii
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + apb4 {
Same comments as other patches. Do not come with your own style, but
adjust to mainline. Do you see this anywhere?
git grep apb4 -- Documentation/devicetree/bindings/clock/
So why coming with something COMPLETELY different?
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-05-15 8:10 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 12:47 [PATCH 00/10] Add support for A9 family clock controller Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 01/10] dt-bindings: clock: Add Amlogic A9 SCMI " Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 02/10] dt-bindings: clock: Add Amlogic A9 PLL " Jian Hu via B4 Relay
2026-05-15 8:09 ` Krzysztof Kozlowski
2026-05-11 12:47 ` [PATCH 03/10] dt-bindings: clock: Add Amlogic A9 peripherals " Jian Hu via B4 Relay
2026-05-14 16:15 ` Jerome Brunet
2026-05-15 8:10 ` Krzysztof Kozlowski [this message]
2026-05-11 12:47 ` [PATCH 04/10] dt-bindings: clock: Add Amlogic A9 AO " Jian Hu via B4 Relay
2026-05-15 8:10 ` Krzysztof Kozlowski
2026-05-11 12:47 ` [PATCH 05/10] clk: amlogic: PLL l_detect signal supports active-high configuration Jian Hu via B4 Relay
2026-05-11 15:47 ` Brian Masney
2026-05-14 15:13 ` Jerome Brunet
2026-05-11 12:47 ` [PATCH 06/10] clk: amlogic: PLL reset signal supports active-low configuration Jian Hu via B4 Relay
2026-05-11 15:21 ` Brian Masney
2026-05-13 3:53 ` Jian Hu
2026-05-14 15:16 ` Jerome Brunet
2026-05-11 12:47 ` [PATCH 07/10] clk: amlogic: Support POWER_OF_TWO for PLL pre-divider Jian Hu via B4 Relay
2026-05-11 15:23 ` Brian Masney
2026-05-14 15:11 ` Jerome Brunet
2026-05-11 12:47 ` [PATCH 08/10] clk: amlogic: Add A9 PLL clock controller driver Jian Hu via B4 Relay
2026-05-11 15:36 ` Brian Masney
2026-05-13 7:25 ` Jian Hu
2026-05-14 16:12 ` Jerome Brunet
2026-05-11 12:47 ` [PATCH 09/10] clk: amlogic: Add A9 peripherals " Jian Hu via B4 Relay
2026-05-11 15:42 ` Brian Masney
2026-05-13 8:50 ` Jian Hu
2026-05-11 12:47 ` [PATCH 10/10] clk: amlogic: Add A9 AO " Jian Hu via B4 Relay
2026-05-11 15:45 ` Brian Masney
2026-05-13 9:19 ` Jian Hu
2026-05-14 16:27 ` Jerome Brunet
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