From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FDFD3F660B for ; Fri, 15 May 2026 16:26:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778862399; cv=none; b=SaiRvoIPuZy1YqfMFVa5CZLbP79mbnR5xNQqOl6BZ0iZBWHfokTmuUm1NCBU+E3GK3bBwnp0i4MRfEdTRAAHPySyZLLMu2CYTpfno2szS2WDbUK+A8dK9XtTyNcfmIgSYANbtBe00UnLI4U15j18jlJKEW0CW+S3DOlLqv7rojU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778862399; c=relaxed/simple; bh=T94SZ4H/vEWxvq2Fldpgqi4a7P/tZbuGeA0n1Ybnq3M=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=KetkwxY9UA4+gbr7faN0gSKWzwloPu/kDoZtaRhL9nkQadUX1obgoSS7fhW8wYK4wUuw9B5QcCMqxqAvf+pof7rxxFUuw1L3MTmnhWewII6dZ/Th3u3Jm/BY6Atjl0b0P7VY7HG56lM7jlRUXryajezL52wWMNODry4o8RtoAko= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TwyxfXn5; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TwyxfXn5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778862399; x=1810398399; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=T94SZ4H/vEWxvq2Fldpgqi4a7P/tZbuGeA0n1Ybnq3M=; b=TwyxfXn5oqJylq3g5+DI68uSSsDPZ7Z594UbmEYW+5sIc2cQVQviALgu zEZ6gGr8Pyh1uIRYjjj9yT5BS4nHD6km6Qu+yzwCxWgaPtcN1QojWtrIf 9ULNDp49EyIabcUu36bGBbvyZSY7DmP/+FVUJvEV5U8UrTpf3bXwrnC3z giyw3VLH/DPoG/L0im1Dz+wpZXG+r0IlpX3mQOjNO7A6egEyFmISFoXhB RXbFX0VkmKSOOVKuRPsWTu7i4tTtB4xQM3Zdl8LXOCJiYfj4QTlwcyJ8M VjYF2XDBpNcVXy2nsyQ8Dretszpq3JUAEg3xg7MfZAj1Nl975oXllLee3 g==; X-CSE-ConnectionGUID: SvywWlL9Q/CFF+6RiQBTPA== X-CSE-MsgGUID: SIkjlcQgSAejoLhEcA9kVQ== X-IronPort-AV: E=McAfee;i="6800,10657,11787"; a="79785219" X-IronPort-AV: E=Sophos;i="6.23,236,1770624000"; d="scan'208";a="79785219" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2026 09:26:38 -0700 X-CSE-ConnectionGUID: ygMJeAFmRdWtGmQgR4BfSg== X-CSE-MsgGUID: 8BE5A4nlT4SdpxicBnPIOQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,236,1770624000"; d="scan'208";a="238857089" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.28]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2026 09:26:31 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V4 00/17] i3c: mipi-i3c-hci: DMA abort, recovery and related improvements Date: Fri, 15 May 2026 19:26:04 +0300 Message-ID: <20260515162621.57719-1-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: 8bit Hi This series improves the robustness of the MIPI I3C HCI DMA mode driver, addressing issues observed during error handling and recovery. Patch 1 ensures suspend always invokes io->suspend. Patches 2-4 fix issues in the existing DMA abort path: preserving the RUN bit during abort per the MIPI specification, blocking enqueue during abort/error, and waiting for ring restart completion. Patches 5-8 improve how partially completed transfer lists are handled during dequeue: moving hci_dma_xfer_done() earlier so completed responses are processed before NoOp replacement, completing transfer lists immediately on error rather than deferring, and detecting when an abort races with transfer completion to avoid restarting the wrong transfer list. Patches 9-11 add Intel-specific quirks for DMA ring abort: a PIO queue reset after abort, and an HC_CONTROL ABORT before the ring-level abort. Patch 12 factors out a reset-and-restore helper from the suspend path for reuse. Patch 13 adds a full DMA recovery path for internal controller errors. When the hardware reports a TID mismatch or the ring becomes stuck, the driver now resets and restores the controller, terminating all in-flight transfers with an error status. Patch 14 makes NoOp command handling observable: instead of discarding NoOp responses, the driver now waits for them to complete and triggers recovery if they fail. Patch 15 adjusts transfer timeout accounting to start from when a transfer actually begins execution rather than when it was queued, preventing premature timeouts behind slow predecessors. Patches 16-17 are minor optimizations: consolidating the DMA command and response ring into a single coherent allocation, and increasing the ring size to the maximum 255 entries to avoid ring-space exhaustion. Changes in V4: i3c: mipi-i3c-hci: Add DMA ring abort/reset quirk for Intel controllers Inline HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET check at call site instead of using a helper function i3c: mipi-i3c-hci: Factor out hci_dma_abort() New patch i3c: mipi-i3c-hci: Add DMA ring abort quirk for Intel controllers Factor out hci_dma_abort() into a preceding patch Make hci_dma_requires_hc_abort_quirk() void; move quirk check to caller i3c: mipi-i3c-hci: Base timeouts on actual transfer start time Rename start_time to start_jiffies i3c: mipi-i3c-hci: Consolidate DMA ring allocation Cache allocation size in xfer_alloc_sz to avoid recomputing in hci_dma_free() Changes in V3: i3c: mipi-i3c-hci: Fix suspend behavior when bus disable falls back to software reset i3c: mipi-i3c-hci: Preserve RUN bit when aborting DMA ring Add Frank's rev'd-by i3c: mipi-i3c-hci: Add DMA-mode recovery for internal controller errors When erroring out transfers, ensure the final transfer of a transfer list is processed last Changes in V2: i3c: mipi-i3c-hci: Fix suspend behavior when bus disable falls back to software reset Always return 0 from suspend callback Amend commit message i3c: mipi-i3c-hci: Preserve RUN bit when aborting DMA ring Improve commit message i3c: mipi-i3c-hci: Prevent DMA enqueue while ring is aborting or in error Improve commit message i3c: mipi-i3c-hci: Wait for DMA ring restart to complete None i3c: mipi-i3c-hci: Move hci_dma_xfer_done() definition Add Frank's Rev'd-by i3c: mipi-i3c-hci: Call hci_dma_xfer_done() from dequeue path Add Frank's Rev'd-by i3c: mipi-i3c-hci: Complete transfer lists immediately on error Rename completing_xfer to final_xfer i3c: mipi-i3c-hci: Avoid restarting DMA ring after aborting wrong transfer Rename completing_xfer to final_xfer i3c: mipi-i3c-hci: Add DMA ring abort/reset quirk for Intel controllers None i3c: mipi-i3c-hci: Add DMA ring abort quirk for Intel controllers None i3c: mipi-i3c-hci: Factor out reset-and-restore helper Drop redundant i3c_hci_sync_irq_inactive(hci) from i3c_hci_reset_and_restore() because it is called by hci->io->suspend() anyway i3c: mipi-i3c-hci: Add DMA-mode recovery for internal controller errors Rename completing_xfer to final_xfer Add hci_dma_xfer_done() before checking for an already complete transfer Improve commit message i3c: mipi-i3c-hci: Wait for NoOp commands to complete Rename completing_xfer to final_xfer Add missing reinit_completion() i3c: mipi-i3c-hci: Base timeouts on actual transfer start time Do not flag the next transfer as started when there is an error which halts the controller Instead flag it started at the end of hci_dma_dequeue_xfer() Use hci_start_xfer() in pio.c i3c: mipi-i3c-hci: Consolidate DMA ring allocation Check for failed allocation before assignments to avoid doing arithmetic with NULL pointers i3c: mipi-i3c-hci: Increase DMA transfer ring size to maximum None Adrian Hunter (17): i3c: mipi-i3c-hci: Fix suspend behavior when bus disable falls back to software reset i3c: mipi-i3c-hci: Preserve RUN bit when aborting DMA ring i3c: mipi-i3c-hci: Prevent DMA enqueue while ring is aborting or in error i3c: mipi-i3c-hci: Wait for DMA ring restart to complete i3c: mipi-i3c-hci: Move hci_dma_xfer_done() definition i3c: mipi-i3c-hci: Call hci_dma_xfer_done() from dequeue path i3c: mipi-i3c-hci: Complete transfer lists immediately on error i3c: mipi-i3c-hci: Avoid restarting DMA ring after aborting wrong transfer i3c: mipi-i3c-hci: Add DMA ring abort/reset quirk for Intel controllers i3c: mipi-i3c-hci: Factor out hci_dma_abort() i3c: mipi-i3c-hci: Add DMA ring abort quirk for Intel controllers i3c: mipi-i3c-hci: Factor out reset-and-restore helper i3c: mipi-i3c-hci: Add DMA-mode recovery for internal controller errors i3c: mipi-i3c-hci: Wait for NoOp commands to complete i3c: mipi-i3c-hci: Base timeouts on actual transfer start time i3c: mipi-i3c-hci: Consolidate DMA ring allocation i3c: mipi-i3c-hci: Increase DMA transfer ring size to maximum drivers/i3c/master/mipi-i3c-hci/cmd.h | 6 + drivers/i3c/master/mipi-i3c-hci/core.c | 82 ++++++-- drivers/i3c/master/mipi-i3c-hci/dma.c | 333 +++++++++++++++++++++++++-------- drivers/i3c/master/mipi-i3c-hci/hci.h | 22 +++ drivers/i3c/master/mipi-i3c-hci/pio.c | 1 + 5 files changed, 354 insertions(+), 90 deletions(-) Regards Adrian