From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BB6B3FD95B for ; Fri, 15 May 2026 16:26:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778862402; cv=none; b=FFOMwpy1JagHJQSVxaU/Ys+5kMWdNwmOojW94bi4n5vHGziSjlP0QUjGXg+t4hhAZqOas0AjNWNLoEa4TmY+wkCsledEhItWhom00ftC1eQuyF8+FLu8NSPQu8pL9InoZEry7XhOdgh+4GMFJcIRZZDlQ59JfPF1z/7GAi8F1Pk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778862402; c=relaxed/simple; bh=dVCJ05IA2LC6vrTUR77jZ+SF61lBLGgMfwXzmINuLFk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Hc1VJZPJc9cTZmJAag0Zqx7/cEvhS2nkIAVIdKg6GLvwy91D1Yjk+RbDlcqP3mdMpnIHF15Jwp/BIUCRdET3Od/OJ0CRCPtP5Dh4pcU5fyRUoyssvAX4NqIL/ZuXe/1CoNpFQxhu6MGzyhCw4UmOwxxDFdl1u6yNS3X7t/J59RQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=J6tf+4U/; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="J6tf+4U/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778862402; x=1810398402; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dVCJ05IA2LC6vrTUR77jZ+SF61lBLGgMfwXzmINuLFk=; b=J6tf+4U/u4tiZgoU9t1j158+lVEUrJrqhDlssA0NG4PLA7Fg0WKCaaE8 yOwgikEFgw231WUM5Y7WfHB4dKiWdS4deydthrO36EnJ77bVBI6SouUzH kOkTlFzEFaP61lwl+AI1bevgg6DJ7GgUrNK9ho7/gTY8bRn344azI/j6z 7IdVvyZLMvrxq72io46aQXMkt0SRto+dJ9lUWuZf2hc19ONbr/v8co4k+ 1f3qI2V4r0C+SIphhJoUhB4hTiQnI4j9k/QUJRvG9I5VTJQ6LapQFa8ZP c2C1gUzO+2jZuEaIp6CUuHgwY8oPVOOAdVxyxzHh3eUIdZLaG+1P7CTXL Q==; X-CSE-ConnectionGUID: cVmvgAFdRqCOQDUqBhmEHQ== X-CSE-MsgGUID: hv9QAnD3TDSwvUu/A7wbnw== X-IronPort-AV: E=McAfee;i="6800,10657,11787"; a="79785236" X-IronPort-AV: E=Sophos;i="6.23,236,1770624000"; d="scan'208";a="79785236" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2026 09:26:42 -0700 X-CSE-ConnectionGUID: oHWmFItpSp6mp+xABDAUWw== X-CSE-MsgGUID: 1IJrWLIbT+up4aUd90OynA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,236,1770624000"; d="scan'208";a="238857167" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.28]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2026 09:26:40 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V4 04/17] i3c: mipi-i3c-hci: Wait for DMA ring restart to complete Date: Fri, 15 May 2026 19:26:08 +0300 Message-ID: <20260515162621.57719-5-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260515162621.57719-1-adrian.hunter@intel.com> References: <20260515162621.57719-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: 8bit Although hci_dma_dequeue_xfer() is serialized against itself via control_mutex, this does not guarantee that a DMA ring restart triggered by a previous invocation has fully completed. When the function is called again in rapid succession, the DMA ring may still be transitioning back to the running state, which may confound or disrupt further state changes. Address this by waiting for the DMA ring restart to complete before continuing. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V4: Add Frank's Rev'd-by Changes in V2 and V3: None drivers/i3c/master/mipi-i3c-hci/dma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mipi-i3c-hci/dma.c index c3da6eab8eae..3b14bc87bdf6 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -617,6 +617,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } /* restart the ring */ + reinit_completion(&rh->op_done); mipi_i3c_hci_resume(hci); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP); @@ -625,6 +626,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, spin_unlock_irq(&hci->lock); + wait_for_completion_timeout(&rh->op_done, HZ); + return did_unqueue; } -- 2.51.0