From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D1D81E4BE for ; Sun, 17 May 2026 20:01:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779048117; cv=none; b=o2LpJoTOVVeadVwET7GZAnTfFMZBPojP4E0xociikV8bY+dV1YSiUbqKKy5cdaOzVS3nLR0RswfhrlLIelxzZHTwbtCJpCq9dovVA/u862Aj0v1KD6MMkKAtAgcEN+hi0gJKc7ZbDK8CEgzWEjBLCfpScGbd3IgNadE9kqefx9k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779048117; c=relaxed/simple; bh=82bNxhwrbXiEnHYLR5E1iH7oA9ITI4bikZeDKjKYr64=; h=Date:Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type; b=IK/m2a8oFTr+P7VwWmnD/khzgUWu1fwcVBM5f90q694xEMxNdq9lBOoO2T6qV3CFO0p3crCGy3CZCp7MsJRn4q5db9WiqeA1E+op+9zcqG9TP7p07PKA5AwZ5GsKxDWg5PEWZgTVHqxOyj53r2k5Cf3JGp0C8ULV6rcwn7IvC7A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NaeGHBJA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NaeGHBJA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D164FC2BCC6; Sun, 17 May 2026 20:01:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779048117; bh=82bNxhwrbXiEnHYLR5E1iH7oA9ITI4bikZeDKjKYr64=; h=Date:From:To:Cc:Subject:References:From; b=NaeGHBJAzbNA9yBDydAHFbXw65x8c8lzpQhpYXNWs2LKJNGpYR/itqQplQPGH3RiD MHu7XacoREk9BDhNFUtzgDr6t1JYFKwp/r6LKML7yDVQ/D+nmdt5jUQbOQw6NuZQSF 03XUeJs2zVYyYPXTVnPwU/TGTooWi+wFESTowg2v41vPCtxS4innkorkQkyA8ze08O hgRgA8aFOGLatn5QhDu9/9KVURi1ifdpgBem7NVf3WnumHDykejR2bx+CrT4uW0Nhk aS7JQNMC3kyNhEFAOqGTC7yjpLESNQlwbNq8mcBndGG5tXpOHzQinNr21QzfWwXurr hVzvhIrkfFGNA== Date: Sun, 17 May 2026 22:01:54 +0200 Message-ID: <20260517194931.276486277@kernel.org> User-Agent: quilt/0.68 From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Michael Kelley , Dmitry Ilvokhin , Radu Rendec , Jan Kiszka , Kieran Bingham , Florian Fainelli , Marc Zyngier Subject: [patch V6 05/16] x86/irq: Suppress unlikely interrupt stats by default References: <20260517194421.705253664@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 From: Thomas Gleixner Unlikely interrupt counters like the spurious vector and the synthetic APIC ICR read retry show up in /proc/interrupts with all counts 0 most of the time. As these are events which should never happen, suppress them by default and enable them for output when they actually happen. This requires a seperate bitmap as the description array is marked __ro_after_init. With that bitmap in place it becomes RO data. Signed-off-by: Thomas Gleixner Tested-by: Michael Kelley Reviewed-by: Radu Rendec --- V5: Move irq_stat_inc_and_enable() here V4: Fix the bad idea of writing to __ro_after_init marked data V3: New patch --- arch/x86/include/asm/hardirq.h | 1 + arch/x86/kernel/apic/apic.c | 2 +- arch/x86/kernel/apic/ipi.c | 2 +- arch/x86/kernel/irq.c | 38 ++++++++++++++++++++++++++++---------- 4 files changed, 31 insertions(+), 12 deletions(-) --- a/arch/x86/include/asm/hardirq.h +++ b/arch/x86/include/asm/hardirq.h @@ -68,6 +68,7 @@ DECLARE_PER_CPU_ALIGNED(struct pi_desc, #define __ARCH_IRQ_STAT #define inc_irq_stat(index) this_cpu_inc(irq_stat.counts[IRQ_COUNT_##index]) +void irq_stat_inc_and_enable(enum irq_stat_counts which); #ifdef CONFIG_X86_LOCAL_APIC #define inc_perf_irq_stat() inc_irq_stat(APIC_PERF) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2114,7 +2114,7 @@ static noinline void handle_spurious_int trace_spurious_apic_entry(vector); - inc_irq_stat(SPURIOUS); + irq_stat_inc_and_enable(IRQ_COUNT_SPURIOUS); /* * If this is a spurious interrupt then do not acknowledge --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -120,7 +120,7 @@ u32 apic_mem_wait_icr_idle_timeout(void) for (cnt = 0; cnt < 1000; cnt++) { if (!(apic_read(APIC_ICR) & APIC_ICR_BUSY)) return 0; - inc_irq_stat(ICR_READ_RETRY); + irq_stat_inc_and_enable(IRQ_COUNT_ICR_READ_RETRY); udelay(100); } return APIC_ICR_BUSY; --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -68,19 +68,24 @@ struct irq_stat_info { const char *text; }; +#define DEFAULT_SUPPRESSED_VECTOR UINT_MAX + #define ISS(idx, sym, txt) [IRQ_COUNT_##idx] = { .symbol = sym, .text = txt } #define ITS(idx, sym, txt) [IRQ_COUNT_##idx] = \ { .skip_vector = idx## _VECTOR, .symbol = sym, .text = txt } -static struct irq_stat_info irq_stat_info[IRQ_COUNT_MAX] __ro_after_init = { +#define IDS(idx, sym, txt) [IRQ_COUNT_##idx] = \ + { .skip_vector = DEFAULT_SUPPRESSED_VECTOR, .symbol = sym, .text = txt } + +static const struct irq_stat_info irq_stat_info[IRQ_COUNT_MAX] = { ISS(NMI, "NMI", " Non-maskable interrupts\n"), #ifdef CONFIG_X86_LOCAL_APIC ISS(APIC_TIMER, "LOC", " Local timer interrupts\n"), - ISS(SPURIOUS, "SPU", " Spurious interrupts\n"), + IDS(SPURIOUS, "SPU", " Spurious interrupts\n"), ISS(APIC_PERF, "PMI", " Performance monitoring interrupts\n"), ISS(IRQ_WORK, "IWI", " IRQ work interrupts\n"), - ISS(ICR_READ_RETRY, "RTR", " APIC ICR read retries\n"), + IDS(ICR_READ_RETRY, "RTR", " APIC ICR read retries\n"), ISS(X86_PLATFORM_IPI, "PLT", " Platform interrupts\n"), #endif #ifdef CONFIG_SMP @@ -121,34 +126,47 @@ static struct irq_stat_info irq_stat_inf #endif }; +static DECLARE_BITMAP(irq_stat_count_show, IRQ_COUNT_MAX) __read_mostly; + static int __init irq_init_stats(void) { - struct irq_stat_info *info = irq_stat_info; + const struct irq_stat_info *info = irq_stat_info; for (unsigned int i = 0; i < ARRAY_SIZE(irq_stat_info); i++, info++) { - if (info->skip_vector && test_bit(info->skip_vector, system_vectors)) - info->skip_vector = 0; + if (!info->skip_vector || (info->skip_vector != DEFAULT_SUPPRESSED_VECTOR && + test_bit(info->skip_vector, system_vectors))) + set_bit(i, irq_stat_count_show); } #ifdef CONFIG_X86_LOCAL_APIC if (!x86_platform_ipi_callback) - irq_stat_info[IRQ_COUNT_X86_PLATFORM_IPI].skip_vector = 1; + clear_bit(IRQ_COUNT_X86_PLATFORM_IPI, irq_stat_count_show); #endif #ifdef CONFIG_X86_POSTED_MSI if (!posted_msi_enabled()) - irq_stat_info[IRQ_COUNT_POSTED_MSI_NOTIFICATION].skip_vector = 1; + clear_bit(IRQ_COUNT_POSTED_MSI_NOTIFICATION, irq_stat_count_show); #endif #ifdef CONFIG_X86_MCE_AMD if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) - irq_stat_info[IRQ_COUNT_DEFERRED_ERROR].skip_vector = 1; + clear_bit(IRQ_COUNT_DEFERRED_ERROR, irq_stat_count_show); #endif return 0; } late_initcall(irq_init_stats); +/* + * Used for default enabled counters to increment the stats and to enable the + * entry for /proc/interrupts output. + */ +void irq_stat_inc_and_enable(enum irq_stat_counts which) +{ + this_cpu_inc(irq_stat.counts[which]); + set_bit(which, irq_stat_count_show); +} + #ifdef CONFIG_PROC_FS /* * /proc/interrupts printing for arch specific interrupts @@ -158,7 +176,7 @@ int arch_show_interrupts(struct seq_file const struct irq_stat_info *info = irq_stat_info; for (unsigned int i = 0; i < ARRAY_SIZE(irq_stat_info); i++, info++) { - if (info->skip_vector) + if (!test_bit(i, irq_stat_count_show)) continue; seq_printf(p, "%*s:", prec, info->symbol);