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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?/VLXRKEG3pUzrjGm37+lbDsjdXPTVvqCUtZc8d9XEljiXxL0J99cQpxX4B2f?= =?us-ascii?Q?JGWkMZAySd5ZotaDvPHPGoFlcGxdBOTuHqNAS4McrHxfSGHM1cliCEZ3iepd?= =?us-ascii?Q?R6zsUby3LG3pxrOOcc6Ylh+xg3u8uIMi0UABsJ794KnI+Fc9Rw0l9EjU1Yqn?= =?us-ascii?Q?PMS6tOVXEFb9LPrHqYgKV/lAQ7YFeISdxaz712jEFcam3VCv4vbT3BV+UVZr?= =?us-ascii?Q?V3E0TIPnqErmVn9EM6QIT2huqzCRZ1WuP5glD2t/XmbYO7Zn2kXdyI7Bm2eE?= =?us-ascii?Q?y9qNGUfXFtlctXF2CuIOs5UGWX8PYGEAdWpgCWRd9mQBitXNHNjMi6Id2Tra?= =?us-ascii?Q?wEpjpSXbMlbazuyCIOXPq1+fkBkex7ZPJKeqlLg9/j2ZSXPiDx9OKP8njM0l?= =?us-ascii?Q?ryGl6kpgU7k0L3gifCTUIQX+3kPewpqES2OdNctd5aLBeuAvCROv9q8fFhb7?= =?us-ascii?Q?hnCs99ZjpIcFzb+Q029TgtcWEeK/Ik9bjXAt9CANyLvrz7+2vxNozxo4YkBg?= =?us-ascii?Q?xpYXHX1L4ybLfxK+uGNxirGw3YrpElQlDB3kUP9k7xgfmgPIcs7wpLmiTSnD?= =?us-ascii?Q?yg2kjItdZD5x6Xh0DWRFc7/DVqeA3+4fMhLH+Drp27VtDcoP7K6zclP0oDFQ?= =?us-ascii?Q?6YPBTVu+M5hA51m3HPsl8wU3nbFjSL61w11ioYCrNyED+fEoqjx1FCD6qCg0?= =?us-ascii?Q?BBnEWQ+JmF6Cc4MrZVkxQUHyQhydQc7d8OsPsOLs3NIoVhO1K4YN3LQ2fLcg?= =?us-ascii?Q?+1nVPrmOzr6DhG3j+y8GMzrmNXkzRDsajmLYr+WsQ2JShO0OhTNPStibkRVW?= =?us-ascii?Q?Qw0BGMveH2hWuVGoOfy3Q2lJ2NSV8mFTtMM3IiTaUuy/SLKSTKPj5IrjGbdz?= =?us-ascii?Q?GKHH+1Sc8fuGSyXQg0KgkUr7QtKGtA67NidFZ74fBVajEh4NHavNT+EYNhVK?= =?us-ascii?Q?K5uXlOQVD7W7y11aemz8ofEYeKgU3ty76R7X+TH/5mGC5T2G0N5SSbJFGWaI?= =?us-ascii?Q?a5gs8jcYgLKt3OwyEK+Oe8N9SWXMmlKtPzAo+z01RMm5dLnYLoX+6/qhAyy5?= =?us-ascii?Q?5VTzSqi1ft0rUEmyBp5p0GaFYOdKf3K1GhzucoemDoNHEqUu5Q647F9MPQ4P?= =?us-ascii?Q?AxwlU6uC6UqqPK9EK9iOcfMJndXOM9q5Y1R7dpwYPDpeY9XUYDOTwl4z4fL8?= =?us-ascii?Q?VbczyjOqT8aNTkpH99Dp4ViTVWHnPxYiTVg6nmdo7iQNr91Jfxnx0KDz0Ebh?= =?us-ascii?Q?m9nmNuEDXB+nVRaJkxAsajbsSnBWEbxBC6WwmMbu/A1aLuaPooL3AlvVphkF?= =?us-ascii?Q?/HAZsTbU7KXwZzYm1FAfRWzaFrm+c5/bATF0RLycL0//7Y6EzIvgBhCNUxD2?= =?us-ascii?Q?lfA41oUA06UMWSzlTLaJmN08X+AfUvlSyl6Xe799aE0xGCBBJew0tEZax8BZ?= =?us-ascii?Q?oNeJbXzUVtEsbaK+j4w04Vf7w3OybBS4HRxG8OjH9jF/PMqzcLLP2IyxnFtu?= =?us-ascii?Q?ov1I/7+/BGSjbUb9IOjb9qeu6M59ste1pVo5rKXFKayeJJvopAE8aywNFUSa?= =?us-ascii?Q?wjQTd68TjzzYQ5j8s/D0G7YJ+Tx2IeHCfFxihDL1UGsGlmOHXQ1v0+6nr+0T?= =?us-ascii?Q?TnTDHUQZaynwEZj0FbHATBdddFrbqnl9n0ATNX4Iq+RWVo81TAg1NerNy6Nu?= =?us-ascii?Q?yJ8Alj5hX8phUql3Z+ct/virGyDFLt5j36ZVstP8bUADWU0cp2Cpa1GIsziJ?= =?us-ascii?Q?bHwJOG1+VA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 15a1c7f3-8f59-41a4-12c3-08deb70ae1f2 X-MS-Exchange-CrossTenant-AuthSource: DS7PR12MB9474.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 07:30:50.2814 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: tPBgXYhmosJRtkfOm7IeXo/c3n1zqfjUyAPLp5ou9r9uvIMoAnkXpMqGkfIPqqD8p+ilZpAcF9QMxpKYRjSDFg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4254 This series adds an arm64 backend for memregion cache invalidation users based on the Arm SMCCC cache clean+invalidate interface. Per DEN0028, this interface targets systems where a Normal Cacheable memory region can be modified in ways that are not handled by usual PE coherency mechanisms, and where VA-based CMOs may be too slow or insufficient for large ranges and/or system-cache implementations. Representative use cases include device-backed memory state transitions where stale CPU/system cache lines must be invalidated reliably (for example secure erase, reset/offline flows, and dynamic memory reconfiguration). Patch 1 introduces the Arm SMCCC cache clean/invalidate function IDs and transient return codes needed by callers [1]. Patch 2 adds an arm64 cache maintenance provider that: - discovers SMCCC support and attributes at init time - registers with the generic cache coherency framework used by cpu_cache_invalidate_memregion() - handles transient BUSY/RATE_LIMITED responses with bounded retries - coalesces waiters when firmware reports a global operation type This patch set does not add a software fallback path; when firmware does not implement the SMCCC cache maintenance interface, the provider is not registered and existing behavior is preserved. Reference: [1] https://developer.arm.com/documentation/den0028/latest Srirangan Madhavan (2): arm64: smccc: add cache clean/invalidate IDs and return codes arm64: mm: add SMCCC-backed cache invalidate provider MAINTAINERS | 1 + arch/arm64/mm/Makefile | 1 + arch/arm64/mm/cache_maint.c | 180 ++++++++++++++++++++++++++++++++ include/linux/arm-smccc.h | 17 ++- tools/include/linux/arm-smccc.h | 17 ++- 5 files changed, 212 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/mm/cache_maint.c base-commit: 3b3bea6d4b9c162f9e555905d96b8c1da67ecd5b -- 2.43.0