From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87AC84508E4 for ; Fri, 22 May 2026 14:20:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459663; cv=none; b=NRRj/7xvesuP3EevL+GRm8COFObtPzxGIW/7wxnH/unEUMU96T8CKgTavwL2oGY1xof536hxR2hb9Ev8qb5We9hQKDd6pxQ/THeHZc6Cyx5FjKNJF2p8VDZpnJ14kvna/15MxQvgy67+QQ/oREoQ35/ZacR9W7tFfU5+5ALHnc4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779459663; c=relaxed/simple; bh=y2zxQ139gHQI3Vzeq3Lsl53kLU/el/9mNHeoQaJgIb8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=T/QduTGoxPz0b2QGecw92fkiwan3MKH0mFtJmsgnfey1h38MgG40Z8Nv+grEZDUfJO+y7V1JDctKW8TpD8IOUFyUPmZQiOYyfnKY9gbJQ+00rjuRo8bRt0/l+FbBBrgCR4W92noBmbpLV0msrUe2HSQZEZjrKlbZYIxDBtXWEqw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=V7oxZJv+; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="V7oxZJv+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D0FAC1F00A3D; Fri, 22 May 2026 14:20:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779459652; bh=oXIK+cBu6urjvTGhsBL+5S0tHUK0ISof8qCbA0I9wM0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=V7oxZJv+MZWhFVDAePYoRiHd0Y1Z2pxNTc0iupY1Lbc5/AT3qsmjUeCUdYSBuBC7N Jsf3dRLSoaK3hrq2tjTAmQNsX7a1K2UHPDNG/pDNdrdAGbxfYCq3DDVqXLQiZjWZfh mSiVR0ltKpAwJV1d+7VNThin5o+u+c6yvB9uD2dI+bd1xGwXhXQL9x+la6GZREgmtk 5KMvsoc+gfF+5Sa7Og/wYYtSeZVHiJIQNcsYMkw1S0sdLQV8N0ngW/p2NR2vuHy97q M2l7UT8R3JtiSvwPxa45EgNhdLrDeN9ZMoED/CVnBLrqAsv7G7xHseP8nqMr9hCX67 H7u8j4b4IBAJQ== From: Arnd Bergmann To: Ingo Molnar Cc: Arnd Bergmann , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Peter Zijlstra , Will Deacon , Boqun Feng , Gary Guo , Yury Norov , Rasmus Villemoes , Boris Ostrovsky , Alexander Usyskin , Tony Nguyen , Przemek Kitszel , x86@kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org Subject: [PATCH 6/8] x86: require minimum 64 byte cache lines Date: Fri, 22 May 2026 16:19:57 +0200 Message-Id: <20260522141959.1071595-7-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260522141959.1071595-1-arnd@kernel.org> References: <20260522141959.1071595-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Arnd Bergmann Later x86-32 CPUs like Pentium-M, K7 and Atom use 64 byte cache lines and are incompatible with kernels built for smaller values of X86_L1_CACHE_SHIFT. Pentium-4 CPUs have 128 byte cache lines but are compatible with cache operations that expect the lines to be 64 bytes. Older CPUs have smaller cache lines of 16 or 32 bytes but work correctly when X86_L1_CACHE_SHIFT is set to a larger value. Remove the per-CPU tuning and always build for 64 or 128 byte cache lines that work correctly in any CPU. Signed-off-by: Arnd Bergmann --- arch/x86/Kconfig.cpu | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 65d887274dd8..4991b633047e 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -180,8 +180,8 @@ config MVIAC7 bool "VIA C7" depends on X86_32 help - Select this for a VIA C7. Selecting this uses the correct cache - shift and tells gcc to treat the CPU as a 686. + Select this for a VIA C7. Selecting this tells gcc to treat the + CPU as a 686. config MATOM bool "Intel Atom" @@ -239,9 +239,7 @@ config X86_INTERNODE_CACHE_SHIFT config X86_L1_CACHE_SHIFT int default "7" if MPENTIUM4 - default "6" if MK7 || MPENTIUMM || MATOM || MVIAC7 || X86_GENERIC || X86_64 - default "4" if MGEODEGX1 - default "5" if MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MVIAC3_2 || MGEODE_LX + default "6" config X86_F00F_BUG def_bool y -- 2.39.5