From: Can Guo <can.guo@oss.qualcomm.com>
To: bvanassche@acm.org, beanhuo@micron.com, peter.wang@mediatek.com,
martin.petersen@oracle.com, mani@kernel.org
Cc: linux-scsi@vger.kernel.org, Can Guo <can.guo@oss.qualcomm.com>,
Alim Akhtar <alim.akhtar@samsung.com>,
Avri Altman <avri.altman@wdc.com>,
"James E.J. Bottomley" <James.Bottomley@HansenPartnership.com>,
Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com>,
Nitin Rawat <quic_nitirawa@quicinc.com>,
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH 2/2] scsi: ufs: core: Add support for static TX Equalization settings
Date: Wed, 27 May 2026 07:40:55 -0700 [thread overview]
Message-ID: <20260527144055.2758170-3-can.guo@oss.qualcomm.com> (raw)
In-Reply-To: <20260527144055.2758170-1-can.guo@oss.qualcomm.com>
Static TX Equalization settings and TX Precode enable indication from DT
properties txeq-preshoot-g[1-6], txeq-deemphasis-g[1-6], and
tx-precode-enable-g6 are board-specific baseline values. Values are
provided as per-lane tuples:
<Host_Lane0 Device_Lane0>, [<Host_Lane1 Device_Lane1>]
Parse DT u32 properties with explicit range checks by using
of_property_count_u32_elems()/of_property_read_u32_array().
When adaptive TX Equalization is used, these static settings are not final:
- If valid settings are retrieved from qTxEQGnSettings/wTxEQGnSettingsExt,
those retrieved settings override static DT settings.
- If retrieval is not available/valid, TX EQTR runs and trained settings
override static DT settings.
So static DT settings are a fallback and are intended for cases where
adaptive TX Equalization is not enabled/used. Adaptive TX Equalization
remains the primary path when enabled.
No behavior changes for platforms that do not provide these properties.
Signed-off-by: Can Guo <can.guo@oss.qualcomm.com>
---
drivers/ufs/core/ufs-txeq.c | 4 +-
drivers/ufs/host/ufshcd-pltfrm.c | 128 +++++++++++++++++++++++++++++++
include/ufs/ufshcd.h | 2 +
3 files changed, 133 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/core/ufs-txeq.c b/drivers/ufs/core/ufs-txeq.c
index 4b264adfdf49..634ec039e129 100644
--- a/drivers/ufs/core/ufs-txeq.c
+++ b/drivers/ufs/core/ufs-txeq.c
@@ -1297,7 +1297,7 @@ int ufshcd_config_tx_eq_settings(struct ufs_hba *hba,
}
params = &hba->tx_eq_params[gear - 1];
- if (!params->is_valid || force_tx_eqtr) {
+ if (!params->is_valid || params->is_static || force_tx_eqtr) {
int ret;
ret = ufshcd_tx_eqtr(hba, params, pwr_mode);
@@ -1310,6 +1310,7 @@ int ufshcd_config_tx_eq_settings(struct ufs_hba *hba,
/* Mark TX Equalization settings as valid */
params->is_valid = true;
params->is_trained = true;
+ params->is_static = false;
params->is_applied = false;
}
@@ -1495,6 +1496,7 @@ static void ufshcd_extract_tx_eq_settings_attrs(struct ufs_hba *hba, u8 gear)
}
params->is_valid = true;
+ params->is_static = false;
}
void ufshcd_retrieve_tx_eq_settings(struct ufs_hba *hba)
diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c
index c2dafb583cf5..2db2103a6ac0 100644
--- a/drivers/ufs/host/ufshcd-pltfrm.c
+++ b/drivers/ufs/host/ufshcd-pltfrm.c
@@ -210,6 +210,132 @@ static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba)
}
}
+static void ufshcd_parse_static_tx_eq_settings(struct ufs_hba *hba)
+{
+ size_t sz = hba->lanes_per_direction * 2;
+ u32 lpd = hba->lanes_per_direction;
+ struct ufshcd_tx_eq_params *params;
+ u32 deemphasis[UFS_MAX_LANES * 2];
+ u32 precode_en[UFS_MAX_LANES * 2];
+ u32 preshoot[UFS_MAX_LANES * 2];
+ struct device *dev = hba->dev;
+ char prop_name[MAX_PROP_SIZE];
+ int i, err, count, gear, lane;
+
+ if (!lpd || lpd > UFS_MAX_LANES) {
+ dev_err(dev, "Invalid lanes-per-direction value (%u) provided\n", lpd);
+ return;
+ }
+
+ for (gear = UFS_HS_G1; gear <= UFS_HS_GEAR_MAX; gear++) {
+ snprintf(prop_name, MAX_PROP_SIZE, "txeq-preshoot-g%d", gear);
+ count = of_property_count_u32_elems(dev->of_node, prop_name);
+ if (count <= 0)
+ continue;
+
+ if (count != sz) {
+ dev_err(dev, "Property %s has invalid count (%d), expecting %zu\n",
+ prop_name, count, sz);
+ continue;
+ }
+
+ err = of_property_read_u32_array(dev->of_node, prop_name, preshoot, sz);
+ if (err) {
+ dev_err(dev, "Failed to read %s property, %d\n",
+ prop_name, err);
+ continue;
+ }
+
+ for (i = 0; i < count; i++) {
+ if (preshoot[i] >= TX_HS_NUM_PRESHOOT) {
+ dev_err(dev, "An invalid TX EQ PreShoot (%d) provided in %s property\n",
+ preshoot[i], prop_name);
+ break;
+ }
+ }
+
+ if (i != count)
+ continue;
+
+ snprintf(prop_name, MAX_PROP_SIZE, "txeq-deemphasis-g%d", gear);
+ count = of_property_count_u32_elems(dev->of_node, prop_name);
+ if (count <= 0) {
+ dev_err(dev, "Missing required %s property\n", prop_name);
+ continue;
+ }
+
+ if (count != sz) {
+ dev_err(dev, "Property %s has invalid count (%d), expecting %zu\n",
+ prop_name, count, sz);
+ continue;
+ }
+
+ err = of_property_read_u32_array(dev->of_node, prop_name, deemphasis, sz);
+ if (err) {
+ dev_err(dev, "Failed to read %s property, %d\n",
+ prop_name, err);
+ continue;
+ }
+
+ for (i = 0; i < count; i++) {
+ if (deemphasis[i] >= TX_HS_NUM_DEEMPHASIS) {
+ dev_err(dev, "An invalid TX EQ DeEmphasis (%d) provided in %s property\n",
+ deemphasis[i], prop_name);
+ break;
+ }
+ }
+
+ if (i != count)
+ continue;
+
+ memset(precode_en, 0, sizeof(precode_en));
+ if (gear == UFS_HS_G6) {
+ snprintf(prop_name, MAX_PROP_SIZE, "tx-precode-enable-g%d", gear);
+ count = of_property_count_u32_elems(dev->of_node, prop_name);
+ if (count > 0) {
+ if (count != sz) {
+ dev_err(dev, "Property %s has invalid count (%d), expecting %zu\n",
+ prop_name, count, sz);
+ continue;
+ }
+
+ err = of_property_read_u32_array(dev->of_node, prop_name,
+ precode_en, sz);
+ if (err) {
+ dev_err(dev, "Failed to read %s property, %d\n",
+ prop_name, err);
+ continue;
+ }
+
+ for (i = 0; i < count; i++) {
+ if (precode_en[i] > 1) {
+ dev_err(dev, "An invalid PrecodeEn (%d) provided in %s property\n",
+ precode_en[i], prop_name);
+ break;
+ }
+ }
+
+ if (i != count)
+ continue;
+ }
+ }
+
+ params = &hba->tx_eq_params[gear - 1];
+ for (lane = 0; lane < lpd; lane++) {
+ params->host[lane].preshoot = preshoot[lane * 2];
+ params->host[lane].deemphasis = deemphasis[lane * 2];
+ params->host[lane].precode_en = precode_en[lane * 2];
+
+ params->device[lane].preshoot = preshoot[lane * 2 + 1];
+ params->device[lane].deemphasis = deemphasis[lane * 2 + 1];
+ params->device[lane].precode_en = precode_en[lane * 2 + 1];
+ }
+
+ params->is_valid = true;
+ params->is_static = true;
+ }
+}
+
/**
* ufshcd_parse_clock_min_max_freq - Parse MIN and MAX clocks freq
* @hba: per adapter instance
@@ -528,6 +654,8 @@ int ufshcd_pltfrm_init(struct platform_device *pdev,
ufshcd_init_lanes_per_dir(hba);
+ ufshcd_parse_static_tx_eq_settings(hba);
+
err = ufshcd_parse_operating_points(hba);
if (err) {
dev_err(dev, "%s: OPP parse failed %d\n", __func__, err);
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index f48d6416e299..c01824576472 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -359,6 +359,7 @@ struct ufshcd_tx_eqtr_record {
* @is_valid: True if parameter contains valid TX Equalization settings
* @is_applied: True if settings have been applied to UniPro of both sides
* @is_trained: True if parameters obtained from TX EQTR procedure
+ * @is_static: True if settings are static
*/
struct ufshcd_tx_eq_params {
struct ufshcd_tx_eq_settings host[UFS_MAX_LANES];
@@ -367,6 +368,7 @@ struct ufshcd_tx_eq_params {
bool is_valid;
bool is_applied;
bool is_trained;
+ bool is_static;
};
/**
--
2.34.1
next prev parent reply other threads:[~2026-05-27 14:41 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260527144055.2758170-1-can.guo@oss.qualcomm.com>
2026-05-27 14:40 ` [PATCH 1/2] dt-bindings: ufs: Document static TX Equalization settings properties Can Guo
2026-05-28 6:18 ` Manivannan Sadhasivam
2026-05-30 11:36 ` Krzysztof Kozlowski
2026-05-27 14:40 ` Can Guo [this message]
2026-05-28 6:13 ` [PATCH 2/2] scsi: ufs: core: Add support for static TX Equalization settings Manivannan Sadhasivam
2026-05-28 7:24 ` Can Guo
2026-05-28 8:16 ` Manivannan Sadhasivam
2026-05-28 8:40 ` Can Guo
2026-05-28 9:29 ` Manivannan Sadhasivam
2026-05-28 9:31 ` Can Guo
2026-05-28 6:18 ` Manivannan Sadhasivam
2026-05-28 7:27 ` Can Guo
[not found] <20260501134418.863432-1-can.guo@oss.qualcomm.com>
2026-05-01 13:44 ` Can Guo
2026-05-14 13:57 ` Bean Huo
2026-05-15 8:12 ` Can Guo
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