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AFNElJ+a0NfMhG+72tkXUXwcRppQbtz1h/bkctBfLu6j29szxHq7npLjGx+5NELKracXi62dXudJrVV2sLFha+Y=@vger.kernel.org X-Gm-Message-State: AOJu0YyIg2YAJaTe8uZCJuyuQK4dAQxF4e8uZyyHHB5dlAfJN3I5N+Mn s2F8ZeJZg0W0Jih7IBmcqgBwKEqpeQFtzUR2hul7bwW+uUKb1RKrv6i5+Hv7H7sCwClJQKeWrN1 keMDmhpHbIA== X-Received: from plbjc6.prod.google.com ([2002:a17:903:25c6:b0:2bd:9b10:8067]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:2b0b:b0:2bd:d7b5:83ed with SMTP id d9443c01a7336-2bf20bdf1a3mr19071465ad.39.1780030380954; Thu, 28 May 2026 21:53:00 -0700 (PDT) Date: Thu, 28 May 2026 21:51:50 -0700 In-Reply-To: <20260529045155.311805-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260529045155.311805-1-irogers@google.com> X-Mailer: git-send-email 2.54.0.823.g6e5bcc1fc9-goog Message-ID: <20260529045155.311805-9-irogers@google.com> Subject: [PATCH v1 08/12] perf vendor events intel: Update lunarlake events from 1.21 to 1.22 From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Adrian Hunter , James Clark , "=?UTF-8?q?Andreas=20F=C3=A4rber?=" , Manivannan Sadhasivam , Dapeng Mi , Thomas Falcon , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Ian Rogers Content-Type: text/plain; charset="UTF-8" The updated events and metrics were published in: https://github.com/intel/perfmon/commit/fae822a0f9318e602902eeb2166b966a28c715f8 Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/lunarlake/cache.json | 20 +++++++++++++++++++ .../arch/x86/lunarlake/pipeline.json | 9 +++++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json b/tools/perf/pmu-events/arch/x86/lunarlake/cache.json index 2db3e8a51fbd..92a3667b4520 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/cache.json @@ -289,6 +289,16 @@ "UMask": "0x2", "Unit": "cpu_atom" }, + { + "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "EventCode": "0x24", + "EventName": "L2_REQUEST.HIT", + "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]", + "SampleAfterValue": "200003", + "UMask": "0x5f", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts the number of total L2 Cache Accesses that resulted in a Miss from a front door request only (does not include rejects or recycles), per core event", "Counter": "0,1,2,3,4,5,6,7", @@ -387,6 +397,16 @@ "UMask": "0x21", "Unit": "cpu_core" }, + { + "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "EventCode": "0x24", + "EventName": "L2_RQSTS.HIT", + "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]", + "SampleAfterValue": "200003", + "UMask": "0x5f", + "Unit": "cpu_core" + }, { "BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.MISS]", "Counter": "0,1,2,3,4,5,6,7,8,9", diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json b/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json index d98723b3cd78..d66eafccebbb 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json @@ -315,6 +315,15 @@ "UMask": "0xfd", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of relative JMP branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.REL_JMP", + "SampleAfterValue": "200003", + "UMask": "0xdf", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", "Counter": "0,1,2,3,4,5,6,7", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index b97d19ae4264..4176d22da1a7 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -22,7 +22,7 @@ GenuineIntel-6-3A,v24,ivybridge,core GenuineIntel-6-3E,v24,ivytown,core GenuineIntel-6-2D,v24,jaketown,core GenuineIntel-6-(57|85),v16,knightslanding,core -GenuineIntel-6-BD,v1.21,lunarlake,core +GenuineIntel-6-BD,v1.22,lunarlake,core GenuineIntel-6-(AA|AC|B5),v1.20,meteorlake,core GenuineIntel-6-1[AEF],v4,nehalemep,core GenuineIntel-6-2E,v4,nehalemex,core -- 2.54.0.823.g6e5bcc1fc9-goog