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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bf239fd84fsm132766305ad.23.2026.06.02.03.16.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 03:16:45 -0700 (PDT) From: phucduc.bui@gmail.com To: Heiko Stuebner , Mark Brown , Liam Girdwood , Krzysztof Kozlowski Cc: Rob Herring , Conor Dooley , Jaroslav Kysela , Takashi Iwai , devicetree@vger.kernel.org, linux-sound@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH v2 2/5] ASoC: rockchip: spdif: Reorder clock enable sequence Date: Tue, 2 Jun 2026 17:16:05 +0700 Message-ID: <20260602101608.45137-3-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260602101608.45137-1-phucduc.bui@gmail.com> References: <20260602101608.45137-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: bui duc phuc Enable the 'hclk' bus clock before the 'mclk' controller clock during runtime resume. The bus clock provides the register access interface, so enable it before the controller clock. This also makes the resume sequence the reverse of the suspend sequence, which keeps the clock ordering consistent. Signed-off-by: bui duc phuc --- NOTE: This patch is compile-tested only. Please help test if you have the relevant Rockchip hardware. Changes in v2: - Clarify in the commit message that the resume sequence becomes the reverse of the suspend sequence. sound/soc/rockchip/rockchip_spdif.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c index 581624f2682e..8de5b76cfe79 100644 --- a/sound/soc/rockchip/rockchip_spdif.c +++ b/sound/soc/rockchip/rockchip_spdif.c @@ -76,16 +76,16 @@ static int rk_spdif_runtime_resume(struct device *dev) struct rk_spdif_dev *spdif = dev_get_drvdata(dev); int ret; - ret = clk_prepare_enable(spdif->mclk); + ret = clk_prepare_enable(spdif->hclk); if (ret) { - dev_err(spdif->dev, "mclk clock enable failed %d\n", ret); + dev_err(spdif->dev, "hclk clock enable failed %d\n", ret); return ret; } - ret = clk_prepare_enable(spdif->hclk); + ret = clk_prepare_enable(spdif->mclk); if (ret) { - clk_disable_unprepare(spdif->mclk); - dev_err(spdif->dev, "hclk clock enable failed %d\n", ret); + clk_disable_unprepare(spdif->hclk); + dev_err(spdif->dev, "mclk clock enable failed %d\n", ret); return ret; } -- 2.43.0