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From: Conor Dooley <conor@kernel.org>
To: Chi-Wen Weng <cwweng.linux@gmail.com>
Cc: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, cwweng@nuvoton.com
Subject: Re: [PATCH 1/2] dt-bindings: spi: Add for Nuvoton MA35D1 SoC QSPI Controller
Date: Wed, 3 Jun 2026 16:24:26 +0100	[thread overview]
Message-ID: <20260603-daybed-absentee-1b64f5caabe0@spud> (raw)
In-Reply-To: <20260603043551.1062112-2-cwweng.linux@gmail.com>

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On Wed, Jun 03, 2026 at 12:35:50PM +0800, Chi-Wen Weng wrote:
> Signed-off-by: Chi-Wen Weng <cwweng.linux@gmail.com>

Missing commit message for one, but why can't your Nuvoton mail be used
here?

Sashiko had two comments about resets and num-cs that looked valid.

> ---
>  .../bindings/spi/nuvoton,ma35d1-qspi.yaml     | 61 +++++++++++++++++++
>  1 file changed, 61 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml
> 
> diff --git a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml
> new file mode 100644
> index 000000000000..f7b9cb52d8e5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/nuvoton,ma35d1-qspi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Nuvoton MA35D1 Quad SPI Controller
> +
> +maintainers:
> +  - Chi-Wen Weng <cwweng@nuvoton.com>
> +
> +allOf:
> +  - $ref: spi-controller.yaml#
> +
> +properties:
> +  compatible:
> +    const: nuvoton,ma35d1-qspi
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        spi@40680000 {
> +            compatible = "nuvoton,ma35d1-qspi";
> +            reg = <0x0 0x40680000 0x0 0x100>;
> +            interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> +            clocks = <&clk QSPI0_GATE>;
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            flash@0 {

Drop this flash node, it serves no purpose here.

pw-bot: changes-requested

Thanks,
Conor.

> +                compatible = "jedec,spi-nor";
> +                spi-max-frequency = <30000000>;
> +                reg = <0>;
> +                spi-rx-bus-width = <4>;
> +                spi-tx-bus-width = <1>;
> +            };
> +        };
> +    };
> +
> -- 
> 2.25.1
> 

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  parent reply	other threads:[~2026-06-03 15:24 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-03  4:35 [PATCH 0/2] Add support for nuvoton ma35d1 qspi controller Chi-Wen Weng
2026-06-03  4:35 ` [PATCH 1/2] dt-bindings: spi: Add for Nuvoton MA35D1 SoC QSPI Controller Chi-Wen Weng
2026-06-03  9:04   ` Mark Brown
2026-06-03  9:29     ` Chi-Wen Weng
2026-06-03 15:24   ` Conor Dooley [this message]
2026-06-04  7:07     ` Chi-Wen Weng
2026-06-04  8:55       ` Conor Dooley
2026-06-04  9:25         ` Chi-Wen Weng
2026-06-03  4:35 ` [PATCH 2/2] spi: Add Nuvoton MA35D1 QSPI controller support Chi-Wen Weng
2026-06-03  9:30   ` Mark Brown
2026-06-03 11:03     ` Chi-Wen Weng

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