From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-177.mta1.migadu.com (out-177.mta1.migadu.com [95.215.58.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E37DF427A05 for ; Tue, 16 Jun 2026 10:02:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.177 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781604147; cv=none; b=DIUjvMZZXobkqFimkiJiMW01R10f59BlWU/tQImxrIoIgmQjO4gVZARGezmUQX3FTxsPq4PNm/P1EIvkYudZsO38nYKyBfnAgu8MiFa6ZQll845IeSeZjqysONtg6TDwsYm6O/lncIoT3qpfi4A+RTZWiYPiHknC00SxiGNEsIg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781604147; c=relaxed/simple; bh=SvVYExW/Q/Hjd30SnIuldyN+ZO8S41XSiJz0Wzrg+oQ=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=miVAXQSBQ6kyD73wSMQR51lMYBXKQNGU9A51PiXdsiJ1/38eKy4egJRxfxPZrxrb+U7mxBWHiv03UklhYqE/yiJdhSduk/SV+9GQV/jC+y5IrNSlWJQ/4BMEFB5GB39nO0KzlLNu/5/IuLIMmVkUsuH/0UXHQBeUvXxCZtLwP1U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=QpUVcH6F; arc=none smtp.client-ip=95.215.58.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="QpUVcH6F" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1781604142; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=9Qu7CbrKux96cswFy7p5Q7ZYOG3xsyjx9q5YsEYvsXY=; b=QpUVcH6F/ST0TrvmnC6KU2K+o0UC2+qyJCidJFScRPBHFT/j/paZws9On0er7VrKfakUSS grBhbYRCFXApI3TuFNtTZVAanzsjAADhxGZXYtCu+F74qNeYf972poLx1nFaqw5LwxGnCW cSZXNROPaN0/IzU/nRt4coLxYzrd4po= From: Enlin Mu To: tglx@kernel.org, linux-kernel@vger.kernel.org, enlin.mu@unisoc.com, enlin.mu@linux.dev Cc: linux-hardening@vger.kernel.org Subject: [PATCH v2] genirq: Add the entropy pool function to the PPI interrupt handler Date: Tue, 16 Jun 2026 18:02:11 +0800 Message-Id: <20260616100211.3068-1-enlin.mu@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT Accelerate the entropy pool initialization process. The function handle_irq_event_percpu adds entropy pool initialization, but this logic is missing in the PPI interrupt handler. I think this was simply an accidental omission. Signed-off-by: Enlin Mu --- v2:updated the commit message --- kernel/irq/chip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index de754db414d1..cbbd7e7d1156 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -926,6 +926,7 @@ void handle_percpu_devid_irq(struct irq_desc *desc) trace_irq_handler_entry(irq, action); res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id)); trace_irq_handler_exit(irq, action, res); + add_interrupt_randomness(irq); } else { bool enabled = cpumask_test_cpu(cpu, desc->percpu_enabled); -- 2.39.5