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From: Michal Pecio <michal.pecio@gmail.com>
To: Xincheng Zhang <zhangxincheng@ultrarisc.com>
Cc: cyrozap@gmail.com, gregkh@linuxfoundation.org,
	linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org,
	mathias.nyman@intel.com
Subject: Re: [PATCH] usb: xhci-pci: Disable 64-bit DMA for VIA VL805
Date: Thu, 25 Jun 2026 02:04:21 +0200	[thread overview]
Message-ID: <20260625020421.2e577a94.michal.pecio@gmail.com> (raw)
In-Reply-To: <20260624070612.337013-1-zhangxincheng@ultrarisc.com>

On Wed, 24 Jun 2026 15:06:12 +0800, Xincheng Zhang wrote:
> Hi Michal,
> 
> On 2026-06-23 12:18 +0200, Michal Pecio wrote:
> > But I don't like this abuse of the quirk. Firstly, it causes
> > unnecessary bouncing on systems with >4GB RAM and no IOMMU.
> > I found other drivers that use DMA_BIT_MASK(36) or even weirder
> > numbers, so it seems that we too could request 64 gigs exactly
> > with a bit of driver refactoring.  
> 
> Thanks for the review. I totally agree that using `DMA_BIT_MASK(36)`
> is a much better approach to avoid bounce buffers and register width
> issues.

By the way, are you sure that 64GB is the magic number and not 1TB?
I booted a common AMD64 box with iommu.forcedac=1 and instantly got
IOMMU faults, but the addresses were truncated to 40 bits, not 36.

I applied 40 bit DMA mask and my VL805 seems to work. I looked into
debugfs and many things are mapped close to 1TB, so I wonder if some
chips are better than others or maybe there are particular workloads
where VL805 truncates something to 36 bits? I tried a few, including
bulk, interrupt, isochronous and USB3 bulk streams.

How was this problem found? Do you have >64GB RAM and no IOMMU?
Or with IOMMU whose driver allocates mappings above 4GB?

Regards,
Michal

  reply	other threads:[~2026-06-25  0:04 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-23  7:32 [PATCH] usb: xhci-pci: Disable 64-bit DMA for VIA VL805 Xincheng Zhang
2026-06-23 10:18 ` Michal Pecio
2026-06-24  5:26   ` Xincheng Zhang
2026-06-24  7:06   ` Xincheng Zhang
2026-06-25  0:04     ` Michal Pecio [this message]
2026-06-25  2:16       ` Xincheng Zhang

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