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Thu, 25 Jun 2026 09:54:52 -0700 From: To: , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v3 02/11] cxl: Split cxl_await_range_active() from media-ready wait Date: Thu, 25 Jun 2026 22:23:58 +0530 Message-ID: <20260625165407.1769572-3-mhonap@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260625165407.1769572-1-mhonap@nvidia.com> References: <20260625165407.1769572-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B075:EE_|IA1PR12MB7759:EE_ X-MS-Office365-Filtering-Correlation-Id: 922a9040-8119-4d3b-3e93-08ded2da8e54 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|82310400026|1800799024|36860700016|7416014|376014|22082099003|18002099003|56012099006|921020|11063799006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: R+VMjHdcVidjMf97akGH1eYIO1aHHV3IMCGMw0wAmEvVRJwG+VrooVnwXxruVbJHu9dc64n4/CIv0iD08WK/0Qh77cQbxNBOb/qpE0Gn1z1bconAQXcXftXgqgHJxJwdqRgVZTU3x5E2WhI49a1RAEW8PChxvJx4thAx0CZXBN60P+ZndFZV//i0KwNjk+ulho6Si0tCjyC/aw2QDJX8e0+yHCZIh1LxJrrPvlXJAQKt3Js9ydULvgqROvMzFdyPFmeQsNpkrohcNz+8d5gKl+rVz1wlS1iA4itrvqD0LZwabpP2llPI0oI2Uu0+B6u4m69jcg5NtqNc88s46jdotFBfJthKlDIijG4/YWy/qmMK8Rk51jTQr2y4GRTHBfxn6kfQwXGk7vOXCgxnQB2r0zlgtpu2ytjj7USYarLDuNARQwyceUjDsQdy2snegLtG X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jun 2026 16:55:26.3963 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 922a9040-8119-4d3b-3e93-08ded2da8e54 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B075.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7759 From: Manish Honap Before accessing CXL device memory after reset or power-on, the driver must ensure media is ready. Not every CXL device implements the CXL Memory Device register group: many Type-2 devices do not. cxl_await_media_ready() reads cxlds->regs.memdev. Access to memdev registers on a Type-2 device that lacks them can result in a kernel panic. Split the HDM DVSEC range-active poll out of cxl_await_media_ready() into a new helper cxl_await_range_active(). Type-2 cxl drivers (vfio-cxl, in-kernel accelerator drivers) that lack the CXLMDEV status register call this directly. cxl_await_media_ready() now calls cxl_await_range_active() for the DVSEC poll, then reads the memory device status as before. The 60 second per-range timeout from cxl_await_media_ready() (media_ready_timeout module param) applies. Export under the CXL namespace. Signed-off-by: Manish Honap --- drivers/cxl/core/pci.c | 35 ++++++++++++++++++++++++++++++----- include/cxl/cxl.h | 2 ++ 2 files changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index c917608c16f9..c44595447bd8 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -142,16 +142,24 @@ static int cxl_dvsec_mem_range_active(struct cxl_dev_state *cxlds, int id) return 0; } -/* - * Wait up to @media_ready_timeout for the device to report memory - * active. +/** + * cxl_await_range_active - Wait for all HDM DVSEC memory ranges to be active + * @cxlds: CXL device state (DVSEC and HDM count must be valid) + * + * For each HDM decoder range reported in the CXL DVSEC capability, waits + * for the range to report MEM INFO VALID (up to 1s per range), then + * MEM ACTIVE (up to media_ready_timeout seconds per range, default 60s). + * Used by cxl_await_media_ready() and by cxl drivers that bind to Type-2 + * devices without the memdev mailbox (e.g. vfio-cxl, accelerator drivers). + * + * Return: 0 if all ranges become valid and active, -ETIMEDOUT if a + * timeout occurs, or a negative errno from config read on failure. */ -int cxl_await_media_ready(struct cxl_dev_state *cxlds) +int cxl_await_range_active(struct cxl_dev_state *cxlds) { struct pci_dev *pdev = to_pci_dev(cxlds->dev); int d = cxlds->cxl_dvsec; int rc, i, hdm_count; - u64 md_status; u16 cap; rc = pci_read_config_word(pdev, @@ -172,6 +180,23 @@ int cxl_await_media_ready(struct cxl_dev_state *cxlds) return rc; } + return 0; +} +EXPORT_SYMBOL_NS_GPL(cxl_await_range_active, "CXL"); + +/* + * Wait up to @media_ready_timeout for the device to report memory + * active. + */ +int cxl_await_media_ready(struct cxl_dev_state *cxlds) +{ + u64 md_status; + int rc; + + rc = cxl_await_range_active(cxlds); + if (rc) + return rc; + md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); if (!CXLMDEV_READY(md_status)) return -EIO; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 440ab09c640e..3dcc034360af 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -232,4 +232,6 @@ int cxl_set_capacity(struct cxl_dev_state *cxlds, u64 capacity); int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u8 *count, resource_size_t *offset, resource_size_t *size); + +int cxl_await_range_active(struct cxl_dev_state *cxlds); #endif /* __CXL_CXL_H__ */ -- 2.25.1