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[83.28.44.19]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-46c1e840eefsm21008147f8f.1.2026.06.25.10.18.55 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Thu, 25 Jun 2026 10:18:56 -0700 (PDT) Date: Thu, 25 Jun 2026 19:18:52 +0200 From: Michal Pecio To: Xincheng Zhang Cc: cyrozap@gmail.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, mathias.nyman@intel.com Subject: Re: [PATCH] usb: xhci-pci: Disable 64-bit DMA for VIA VL805 Message-ID: <20260625191852.0a8d511c.michal.pecio@gmail.com> In-Reply-To: <178235378952.3114334.15752812276771065417.b4-reply@b4> References: <20260623121847.53749028.michal.pecio@gmail.com> <20260624070612.337013-1-zhangxincheng@ultrarisc.com> <20260625020421.2e577a94.michal.pecio@gmail.com> <178235378952.3114334.15752812276771065417.b4-reply@b4> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 25 Jun 2026 10:16:29 +0800, Xincheng Zhang wrote: > I re-tested this on our side and collected more details. The machine > is an UltraRISC DP1000 riscv64 system with a VIA VL805/806 controller: > > 0002:01:00.0 USB controller [0c03]: VIA Technologies, Inc. VL805/806 xHCI USB 3.0 Controller [1106:3483] (rev 01) > > The booted kernel was built with xHCI debug enabled and with the VL805 > XHCI_NO_64BIT_SUPPORT quirk removed, so the controller was allowed to > use the normal AC64/64-bit DMA path. > > This is a no-IOMMU setup, and the command line does not include > iommu.forcedac. > > The system has about 64 GB of RAM: > > MemTotal: 65837388 kB > > With the 64-bit DMA path enabled, xHCI setup logged DMA addresses > above 0x1000000000: > > xhci_hcd 0002:01:00.0: Enabling 64-bit DMA addresses. > xhci_hcd 0002:01:00.0: // Device context base array address = 0x0x0000001075cef000 (DMA), (____ptrval____) (virt) > xhci_hcd 0002:01:00.0: First segment DMA is 0x0x0000000108961000 > xhci_hcd 0002:01:00.0: ERST deq = 64'h1075ca7000 > xhci_hcd 0002:01:00.0: Slot 1 output ctx = 0x0x0000001075387000 (dma) > xhci_hcd 0002:01:00.0: Output Context DMA address = 0x1075387000 > > Shortly afterwards the controller stopped responding: > > xhci_hcd 0002:01:00.0: Command timeout, USBSTS: 0x00000000 Right, your addresses barely exceed the 36 bit limit. And I found why my chip behaved differently - 40 bit DMA was a firmware upgrade. After downgrading my controller from 00013704 to 00013600 it truncates addresses to 36 bits and fails like yours. And it's a pretty nasty bug, because some of those accesses are writes to scratchpad buffers, so without IOMMU the chip corrupts unrelated memory below 64GB. You can check your FW version with this one-liner: lspci -d 1106:3483 -xxx | awk '/^50:/ { print "VL805 FW version: " $5 $4 $3 $2 }' More about VL805 firmwares: https://github.com/jpmorrison/VL805 One could ask whether 36 bits is low enough for all VL805, but I think it is because the bug is hard not to notice and nobody ever reported it on systems with less than 64 GB of RAM, even though 16 or 32 GB without IOMMU was a common option in DDR3 generation PCs, which is also about the era when this controller was introduced. Regards, Michal