[RFC 0/3] powerpc/perf: Add Device Tree based PMU description framework

[Shivani Nittor <shivani@linux.ibm.com>]

PowerPC has a Performance Monitoring Unit (PMU) infrastructure which provides
comprehensive performance monitoring capabilities at the processor level. The
PMU includes programmable counters (PMCs) and control registers (MMCRs) that
enable detailed performance analysis and profiling.

The PowerPC PMU consists of 6 Performance Monitor Counters (PMCs), where PMC1-4
are fully programmable and can monitor any supported event, while PMC5 and PMC6
are dedicated to counting instructions and cycles respectively. The PMU is
controlled through 5 Monitor Mode Control Registers (MMCRs) that configure
event selection, sampling modes, thresholds, and other monitoring parameters.

This patchset enables the PowerPC PMU by providing a device tree specification
that describes the PMU hardware capabilities, event encoding format, register
mappings, and event constraints. The device tree approach allows firmware
(OPAL/skiboot) to communicate PMU capabilities to the kernel dynamically,
enabling better hardware abstraction and forward compatibility.

PMU Hardware Components:
The PowerPC PMU provides the following hardware components:
- 6 Performance Monitor Counters (PMC1-PMC6)
 * PMC1-4: Programmable counters (32-bit, any event)
 * PMC5: Fixed counter for instructions (32-bit)
 * PMC6: Fixed counter for cycles (32-bit)
- 5 Monitor Mode Control Registers
 * MMCR0 (SPR 795): Primary control register
 * MMCR1 (SPR 798): Event selection and configuration
 * MMCR2 (SPR 785): Extended event configuration
 * MMCR3 (SPR 754): Additional event source selection
 * MMCRA (SPR 0x312): Sampling and marking control

Event Encoding Format:
The device tree describes how 64-bit event codes are decomposed into fields
that map to specific bits in the MMCR registers. Key encoding fields include:
- PMCxSEL: 8-bit event selector (256 events per PMC)
- PMCxUNIT: 4-bit unit selector for event source
- PMCxCOMB: 2-bit combine mode for multi-counter operations
- THRESH_SEL/START/STOP: Threshold-based event filtering
- SDAR_MODE: Data address sampling configuration
- MARK: Instruction marking for sampling
- L2L3_SELECT: Cache event selection
- IFM: Instruction fetch marking mode

Event Constraints:
The PMU enforces several hardware constraints that are described in the DTS:
- Counter restrictions: PMC5 limited to instructions (0x500fa), PMC6 limited
 to cycles (0x600f4)
- Sampling constraints: Events with sampling require specific bit patterns
- Threshold constraints: Threshold events require coordinated MMCR field values
- Cache constraints: Cache events restricted to specific units (6,7,8,9) and
 require PMC4 for certain operations
- EBB (Event-Based Branching) constraints: EBB events require PMC assignment
- BHRB (Branch History Rolling Buffer) constraints: BHRB requires EBB enabled
- L1 qualifier constraints: L1 cache qualifiers for load/store filtering
- Radix scope constraints: Radix page table scope qualification

PMU Events Information:
The device tree includes definitions for common performance events such as:
- Core events: cycles, instructions, dispatch/execution stalls
- Branch events: branches, branch-misses, branch predictions
- Cache events: L1/L2/L3 hits and misses for data and instructions
- TLB events: DTLB and ITLB misses
- Memory events: load/store operations and cache reloads

The kernel discovers the PMU configuration in the device tree at the "pmus"
device node which contains a "pmu_dts@0" child node with compatible field
"ibm,power-pmu".

Parsing of the PMU Information:
To parse the PMU configuration, the kernel discovers the "pmus" node and
walks through the PMU definition, extracting:
- Hardware capabilities (number of PMCs, MMCRs)
- SPR (Special Purpose Register) definitions
- Event code format and field mappings
- MMCR bit field configurations
- Event constraints and restrictions
- Pre-defined event list with codes and descriptions

Here is an excerpt of the DTS showing the PMU node structure:
pmus {
	#address-cells = <1>;
	#size-cells = <0>;

	pmu_dts@0 {
		compatible = "ibm,power-pmu";
		reg = <0>;
		pmu-name = "POWER10 PMU";
		pmu-version = "PowerISA 3.1";
		platform = "power10";
		status = "okay";
		nr_pmc = <6>;
		nr_mmcr = <5>;

		sprs {
			pmcs {
				pmc1 {
					sprn = <787>;
					register-width = <32>;
					privilege = "hv";
					programmable = <1>;
					event = "any";
					status = "okay";
				};
				[...]
			};
			mmcr {
				mmcr0 {
					sprn = <795>;
					register-width = <64>;
					privilege = "hv";
					status = "okay";
				};
				[...]
			};
		};

		evt_code_format {
			compatible = "ibm,power-pmu";

			PMCxSEL {
				description = "PMC event selector (256 possible events per PMC)";
				bits = <0 7>;
				length = <8>;
				mmcr = <1>;
				target_field_base = <32>;
				target_field_shift = <8>;
			};
			[...]
		};

		constraints {
			pmc-constraints {
				max-counter = <6>;

				restricted-counters-5 {
					pmc = <5>;
					valid-events = <0x00000000 0x000500fa>;
				};

				restricted-counters-6 {
					pmc = <6>;
					valid-events = <0x00000000 0x000600f4>;
				};
			};
			[...]
		};

		events {
			cycles {
				event_code = <0x600f4>;
				event-category = "core";
				event-class = "primary";
				description = "Number of processor cycles";
				status = "okay";
			};
			instructions {
				event_code = <0x500fa>;
				event-category = "core";
				event-class = "primary";
				description = "Number of instructions completed";
				status = "okay";
			};
			[...]
		};
	};
};

From the device tree, the kernel parses the PMU hardware description, event
encoding format, constraints, and pre-defined events.

After parsing the PMU configuration, the PMU and its events are registered
with the kernel's perf subsystem, making them available for performance
monitoring and profiling.

This series depends on the corresponding skiboot patches:
https://github.com/maddy-kerneldev/skiboot/commit/783e33f17f13412b89b774124cef0988c0578829

Comments/feedback/suggestions are welcome.

Next Steps:
1) Add DTS support for peripheral and unit-specific PMU events.
2) Extend the DTS schema for additional MMCR registers and controls.
3) Support advanced PMU features such as BHRB.
4) Feedback from Community

Shivani Nittor (3):
  powerpc/perf: Register PMU from device tree and expose events
  powerpc/perf: Add DTS-based MMCR computation
  powerpc/perf: Add DTS-based event constraints

 arch/powerpc/include/asm/dts_pmu.h    |  82 ++++
 arch/powerpc/perf/Makefile            |   4 +-
 arch/powerpc/perf/core-book3s.c       |  12 +-
 arch/powerpc/perf/dts_pmu.c           | 536 ++++++++++++++++++++++++++
 arch/powerpc/perf/internal.h          |   1 +
 arch/powerpc/perf/isa207-common.c     | 262 +++++++++++++
 arch/powerpc/perf/isa207-common.h     |   4 +
 arch/powerpc/platforms/powernv/opal.c |  15 +
 8 files changed, 914 insertions(+), 2 deletions(-)
 create mode 100644 arch/powerpc/include/asm/dts_pmu.h
 create mode 100644 arch/powerpc/perf/dts_pmu.c

-- 
2.54.0