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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF000026C6.mail.protection.outlook.com (10.167.244.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.181.6 via Frontend Transport; Mon, 29 Jun 2026 15:41:48 +0000 Received: from Satlexmb09.amd.com (10.181.42.218) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Mon, 29 Jun 2026 10:41:33 -0500 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb09.amd.com (10.181.42.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Mon, 29 Jun 2026 08:36:11 -0700 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v3 04/22] iommu/amd: Introduce IOMMUFD vIOMMU support for AMD Date: Mon, 29 Jun 2026 15:35:17 +0000 Message-ID: <20260629153535.15775-5-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260629153535.15775-1-suravee.suthikulpanit@amd.com> References: <20260629153535.15775-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb09.amd.com (10.181.42.218) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C6:EE_|IA0PR12MB8840:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f602e55-d0ed-4860-5108-08ded5f4ee74 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|23010399003|36860700016|7416014|376014|6133799003|11063799006|18002099003|22082099003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KCeeZA550BFpXP1OyhAeOFIf3A2cP3+PRvuK6V1erJDkCeJYiEwtCZUx815tOf8q98qu6yCBkK9I/w4c773L0uZfUzJwnWjV0aropJ5LxOzVCDpio5SVlxji7QwTrCZuNCgrV2tyjT+vV/bPWIZm5FVh0CPQggNtwT9KJo+hyXe4a4EurJFBpCi+iIw/PxZ1f9mfe22tWxptiyuUZDiLo26XSEiD5NMm4qSbFfOi5rxADM8Y/ZwFtoISDQMsutHBJTo33ju7AzHPJoPeJoIB24xkJzJKx96xpW4HCK3HWjAfMZ5HJxDVyrydUGslo8hCUZOju0jv/S7u26rSG6ETcWD5Je9iIFRtmDKunKd1zUH8o/0fHkjjM8W/36rnks7ERna1yNuu1l4rw9XQGjLnMxi6sEkil95jXrLj/Bwde0bsM8AjvqEPD7CVuJ56N2Qz X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jun 2026 15:41:48.1260 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f602e55-d0ed-4860-5108-08ded5f4ee74 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C6.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8840 Introduce a new enum iommu_viommu_type (IOMMU_VIOMMU_TYPE_AMD) for AMD vIOMMU along with the struct iommu_viommu_amd, which is used to initialize IOMMUFD vIOMMU instance when calling struct iommu_ops.viommu_init(). Also, hook up struct iomufd_viomu_ops.alloc_domain_nested to connect nested domain allocation with AMD vIOMMU implementation. Additional initialization will be added in subsequent patches. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/iommufd.c | 4 ++++ include/uapi/linux/iommufd.h | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index 52300b867c1f..eee29c26169a 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -34,6 +34,9 @@ void *amd_iommufd_hw_info(struct device *dev, u32 *length, enum iommu_hw_info_ty size_t amd_iommufd_get_viommu_size(struct device *dev, enum iommu_viommu_type viommu_type) { + if (!amd_iommu_viommu || (viommu_type != IOMMU_VIOMMU_TYPE_AMD)) + return 0; + return VIOMMU_STRUCT_SIZE(struct amd_iommu_viommu, core); } @@ -73,5 +76,6 @@ static void amd_iommufd_viommu_destroy(struct iommufd_viommu *viommu) * struct iommufd_viommu_ops - vIOMMU specific operations */ static const struct iommufd_viommu_ops amd_viommu_ops = { + .alloc_domain_nested = amd_iommu_alloc_domain_nested, .destroy = amd_iommufd_viommu_destroy, }; diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index e998dfbd6960..52bcd92975da 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -1052,6 +1052,7 @@ struct iommu_fault_alloc { * @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type * @IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM * SMMUv3) enabled ARM SMMUv3 type + * @IOMMU_VIOMMU_TYPE_AMD: AMD HW-vIOMMU type */ enum iommu_viommu_type { IOMMU_VIOMMU_TYPE_DEFAULT = 0, @@ -1062,6 +1063,7 @@ enum iommu_viommu_type { * VMM must wire the HYP_OWN bit to 0 in guest VINTF_CONFIG register */ IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2, + IOMMU_VIOMMU_TYPE_AMD = 3, }; /** @@ -1080,6 +1082,14 @@ struct iommu_viommu_tegra241_cmdqv { __aligned_u64 out_vintf_mmap_length; }; +/** + * struct iommu_viommu_amd - AMD vIOMMU Interface (IOMMU_VIOMMU_TYPE_AMD) + * @out_vfmmio_mmap_offset: (out) mmap offset for vIOMMU VF-MMIO + */ +struct iommu_viommu_amd { + __aligned_u64 out_vfmmio_mmap_offset; +}; + /** * struct iommu_viommu_alloc - ioctl(IOMMU_VIOMMU_ALLOC) * @size: sizeof(struct iommu_viommu_alloc) -- 2.34.1