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[9.244.8.156]) by smtp.gmail.com with ESMTPSA id af79cd13be357-92e80162220sm268889985a.25.2026.07.02.10.34.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2026 10:34:58 -0700 (PDT) From: Enzo Adriano To: Junhui Liu Cc: Andre Przywara , Brian Masney , Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC 7/8] clk: sunxi-ng: a733: Add bus clock gates Date: Thu, 2 Jul 2026 13:34:54 -0400 Message-ID: <20260702173454.855897-1-enzo.adriano.code@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260310-a733-clk-v1-7-36b4e9b24457@pigmoral.tech> References: <20260310-a733-clk-v1-7-36b4e9b24457@pigmoral.tech> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Junhui, Following Andre's suggestion I went through the bus gates in this patch and compared every register offset and bit position against the public A733 User Manual V0.92. Findings below; everything not listed matched the manual (122 of the 135 gate entries verified clean). 1) UART1-UART6 gate bits look wrong: > +static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb_uart_hws, 0xe04, BIT(1), 0); > +static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb_uart_hws, 0xe08, BIT(2), 0); > +static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb_uart_hws, 0xe0c, BIT(3), 0); > +static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb_uart_hws, 0xe10, BIT(4), 0); > +static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb_uart_hws, 0xe14, BIT(5), 0); > +static SUNXI_CCU_GATE_HWS(bus_uart6_clk, "bus-uart6", apb_uart_hws, 0xe18, BIT(6), 0); Each UART has its own BGR register, and in every one of them the gating bit is bit 0. Manual section 4.1.6.141 (0x0E04 UART1 Bus Gating Reset Register): bit 16 "UART1_RST", bits 15:1 reserved ("/"), bit 0 "UART1_GATING - Gating Clock for UART1, 0: Mask, 1: Pass". Sections 4.1.6.142-4.1.6.146 have the same layout for UART2-UART6. So these six entries should all use BIT(0); as written, enabling any of bus-uart1..6 sets a reserved bit and the UART clock stays gated. (bus-uart0 at 0xe00 BIT(0) and the uartN resets at bit 16 all match the manual.) 2) SYSDAP gate offset looks wrong: > +static SUNXI_CCU_GATE_HWS(bus_sysdap_clk, "bus-sysdap", apb1_hws, > + 0x88c, BIT(0), 0); Manual section 4.1.6.92 puts SYSDAP_BGR_REG at 0x07AC (bit 16 "SYSDAP_RST", bit 0 "SYSDAP_GATING"), and patch 8/8's reset map already uses { 0x7ac, BIT(16) } for RST_BUS_SYSDAP, so the gate here presumably wants 0x7ac as well. There is no CCU register at 0x88C in the manual. 3) Gates without a register in the public manual (V0.92) - these could use a short provenance note near the entry, as discussed for other IDs: - bus-spi4 (0x0F2C) - bus-sgpio (0x1064) - bus-lpc (0x1084) - bus-gmac1 (0x142C) [same question as the GMAC1 clock IDs] - bus-tcon-lcd2 (0x1514, and the tcon-lcd2 mod clock at 0x1510) - the manual documents only VO0_TCONLCD0 (0x1500/0x1504) and VO0_TCONLCD1 (0x1508/0x150C) - mbus-gmac1 (0x05E4 bit 12) - bit 12 is not described in the MBUS Gate Enable Register section The remaining bus/mbus gate entries in this patch all match the manual's offsets and bit positions. Thanks, Enzo