From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from confino.investici.org (confino.investici.org [93.190.126.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCC1B333429 for ; Sun, 5 Jul 2026 19:23:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.190.126.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783279422; cv=none; b=L8SPC0I9YVk7Ic/pGeX0v3UCTY1q32ZVrPaaYr3DNrDKEeJ6VMtDmEUyw9OdZtAPISkt26jkmpbPwDGU2j+BRWjZqC49VsiiumZ0FR8a1fQo9MntnQ6YxpWa0BZkrwh/X9SGeQPnrsAV+UyoO1bzpdiFH1VNPtUOFCogkzDtF0A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783279422; c=relaxed/simple; bh=lEDVawoz8pCpSFKJB2a7fjjgMvN86IrPsxRP88Js+aQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=n5sc36cuPvH36sgAGg7iHoYtErnBqimEsp6gVeM8BIuYqjRZpcAh3af746iI13I/7bF+yOGIGcrJPSn/CyvEztlyBwgSXmw9A0lSuCDQAYEFGGRxWe/YvR62iu3veHHj47PiqPdNSX+CJDfQF+MBQTTswukYjTud1UMHBOd12Tw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=grrlz.net; spf=pass smtp.mailfrom=grrlz.net; dkim=pass (1024-bit key) header.d=grrlz.net header.i=@grrlz.net header.b=Hv02HQZW; arc=none smtp.client-ip=93.190.126.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=grrlz.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=grrlz.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=grrlz.net header.i=@grrlz.net header.b="Hv02HQZW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=grrlz.net; s=stigmate; t=1783279418; bh=IY2m2ey8ZprxeXCeFi5qViLre80OB0BxgZ9ZCI0maBs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Hv02HQZWmCuBTHfJFhvqmXiH5SKCpGNo7McfgpddZNtl/IQdhVgK2AcxE9+82FKa0 JAEgERuhKnOXcI7K+ZZPP/B8SZirxfZ/cQdCKuNEq7x7N15db7Hs0L/wziokm1z1St ps1YzznStRcHi97umffoJIOTPMuSxQBnGomNU7TM= Received: from mx1.investici.org (unknown [127.0.0.1]) by confino.investici.org (Postfix) with ESMTP id 4gtcpy1v2Xz10xb; Sun, 05 Jul 2026 19:23:38 +0000 (UTC) Received: by mx1.investici.org (Postfix) id 4gtcpx5NJ9z10wg; Sun, 05 Jul 2026 19:23:37 +0000 (UTC) From: Bradley Morgan To: Catalin Marinas , Will Deacon , Bradley Morgan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] arm64: sleep: assert compute_mpidr_hash registers are distinct Date: Sun, 5 Jul 2026 19:23:30 +0000 Message-ID: <20260705192331.23150-2-include@grrlz.net> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260705192331.23150-1-include@grrlz.net> References: <20260705192331.23150-1-include@grrlz.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Turn the documented register distinctness requirement into an error at build time instead of silent corruption. Signed-off-by: Bradley Morgan --- arch/arm64/kernel/sleep.S | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S index f093cdf71be1..e112b8537f10 100644 --- a/arch/arm64/kernel/sleep.S +++ b/arch/arm64/kernel/sleep.S @@ -35,8 +35,22 @@ * Output register: dst * Note: input and output registers must be disjoint register sets (eg: a macro instance with mpidr = x1 and dst = x1 is invalid) + This is enforced at build time by the assertions below. */ + .macro mpidr_hash_assert_distinct reg, regs:vararg + .irp r, \regs + .ifc \reg, \r + .error "compute_mpidr_hash: register arguments must be distinct" + .endif + .endr + .endm + .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask + /* \dst is written before any input is consumed */ + mpidr_hash_assert_distinct \dst, \rs0, \rs1, \rs2, \rs3, \mpidr, \mask + /* \mpidr and \mask are clobbered while other inputs are still live */ + mpidr_hash_assert_distinct \mpidr, \rs0, \rs1, \rs2, \rs3, \mask + mpidr_hash_assert_distinct \mask, \rs1, \rs2, \rs3 and \mpidr, \mpidr, \mask // mask out MPIDR bits and \dst, \mpidr, #0xff // mask=aff0 lsr \dst ,\dst, \rs0 // dst=aff0>>rs0 -- 2.53.0