From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from confino.investici.org (confino.investici.org [93.190.126.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54F103559C9 for ; Sun, 5 Jul 2026 19:23:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.190.126.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783279421; cv=none; b=DMt9OKofRhuoPVFELpA0Y/OwiaMXV6WPsDKLI0kqb1tSfAmTW6mmvXh+skrovLevLPLTQHcdVt58iYI+pFjx67i5dznLpCpMOEJbr2i2SOiJdOyK1iQuX25YZbB0ZJMd1e/W7RTpzBIndgp41ul5w6+p0cfM+uC9Dm3jV6V/seE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783279421; c=relaxed/simple; bh=zHYRYYbhp2zlC4uWUjKo2q5LlwIkGmpN0sPrDG43fX8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=T3vDR2huCZo51HJDsSweXCkM0yn0LZMxnRcFiPfU4woUYPp1GXlI423x0Yj+IPe4Hc/ZpBJfTDDH2VpzBgl3jn7UicLceCxFbg3B5iqVeWPpGYYaCBT+N2V+tJuwYWVhTY4SY8dZCfXuUC4KicVammKw8QzP8LYP77WZyq1GpUw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=grrlz.net; spf=pass smtp.mailfrom=grrlz.net; dkim=pass (1024-bit key) header.d=grrlz.net header.i=@grrlz.net header.b=o7YpzpWs; arc=none smtp.client-ip=93.190.126.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=grrlz.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=grrlz.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=grrlz.net header.i=@grrlz.net header.b="o7YpzpWs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=grrlz.net; s=stigmate; t=1783279419; bh=fbSruFJvwcJrm9Np0k2TBS8pdvnZhYTtboREcCieCvM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o7YpzpWs4B2dC5RkIu5471ohJxZ/iDiv8mWlAD+iNAzGhhRb+Etmu+n9J8kQqRCw0 oEsHC4cp2teZBzlQ7/+3Ur8Sh3RtBnUgG3dvB8thg9Tli8wVPGWgw5vmilzE85qwGc 0OpUMGy3Q8/qP6hkSeQ6UxPhda4Pn2DNF47kGmxI= Received: from mx1.investici.org (unknown [127.0.0.1]) by confino.investici.org (Postfix) with ESMTP id 4gtcpz0Qc4z10yF; Sun, 05 Jul 2026 19:23:39 +0000 (UTC) Received: by mx1.investici.org (Postfix) id 4gtcpy2vNbz10y4; Sun, 05 Jul 2026 19:23:38 +0000 (UTC) From: Bradley Morgan To: Catalin Marinas , Will Deacon , Bradley Morgan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] arm64: sleep: dedup the sleep_save_stash slot lookup Date: Sun, 5 Jul 2026 19:23:31 +0000 Message-ID: <20260705192331.23150-3-include@grrlz.net> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260705192331.23150-1-include@grrlz.net> References: <20260705192331.23150-1-include@grrlz.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Both __cpu_suspend_enter() and _cpu_resume() open code the same MPIDR hash lookup. Factor it into a get_sleep_stash_slot macro. Signed-off-by: Bradley Morgan --- arch/arm64/kernel/sleep.S | 55 +++++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 25 deletions(-) diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S index e112b8537f10..8820a131aef7 100644 --- a/arch/arm64/kernel/sleep.S +++ b/arch/arm64/kernel/sleep.S @@ -64,6 +64,31 @@ lsr \mask ,\mask, \rs3 orr \dst, \dst, \mask // dst|=(aff3>>rs3) .endm + +/* + * Compute the address of the current CPU's entry in sleep_save_stash, + * i.e. &sleep_save_stash[hash(MPIDR_EL1)]. + * + * @slot: output register + * + * Clobbers: x2 - x8 + */ + .macro get_sleep_stash_slot slot + mpidr_hash_assert_distinct \slot, x2 + mrs x3, mpidr_el1 + adr_l x2, mpidr_hash + ldr x8, [x2, #MPIDR_HASH_MASK] + /* + * Following code relies on the struct mpidr_hash + * members size. + */ + ldp w4, w5, [x2, #MPIDR_HASH_SHIFTS] + ldp w6, w7, [x2, #(MPIDR_HASH_SHIFTS + 8)] + compute_mpidr_hash x2, x4, x5, x6, x7, x3, x8 + ldr_l \slot, sleep_save_stash + add \slot, \slot, x2, lsl #3 + .endm + /* * Save CPU state in the provided sleep_stack_data area, and publish its * location for cpu_resume()'s use in sleep_save_stash. @@ -88,19 +113,8 @@ SYM_FUNC_START(__cpu_suspend_enter) mov x2, sp str x2, [x0, #SLEEP_STACK_DATA_SYSTEM_REGS + CPU_CTX_SP] - /* find the mpidr_hash */ - ldr_l x1, sleep_save_stash - mrs x7, mpidr_el1 - adr_l x9, mpidr_hash - ldr x10, [x9, #MPIDR_HASH_MASK] - /* - * Following code relies on the struct mpidr_hash - * members size. - */ - ldp w3, w4, [x9, #MPIDR_HASH_SHIFTS] - ldp w5, w6, [x9, #(MPIDR_HASH_SHIFTS + 8)] - compute_mpidr_hash x8, x3, x4, x5, x6, x7, x10 - add x1, x1, x8, lsl #3 + /* find this CPU's slot in sleep_save_stash */ + get_sleep_stash_slot x1 str x0, [x1] add x0, x0, #SLEEP_STACK_DATA_SYSTEM_REGS @@ -131,18 +145,9 @@ SYM_FUNC_START(_cpu_resume) mov x0, x19 bl finalise_el2 - mrs x1, mpidr_el1 - adr_l x8, mpidr_hash // x8 = struct mpidr_hash virt address - - /* retrieve mpidr_hash members to compute the hash */ - ldr x2, [x8, #MPIDR_HASH_MASK] - ldp w3, w4, [x8, #MPIDR_HASH_SHIFTS] - ldp w5, w6, [x8, #(MPIDR_HASH_SHIFTS + 8)] - compute_mpidr_hash x7, x3, x4, x5, x6, x1, x2 - - /* x7 contains hash index, let's use it to grab context pointer */ - ldr_l x0, sleep_save_stash - ldr x0, [x0, x7, lsl #3] + /* grab this CPU's context pointer from sleep_save_stash */ + get_sleep_stash_slot x0 + ldr x0, [x0] add x29, x0, #SLEEP_STACK_DATA_CALLEE_REGS add x0, x0, #SLEEP_STACK_DATA_SYSTEM_REGS /* load sp from context */ -- 2.53.0