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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Suraj Gupta , Marek Vasut , Tomi Valkeinen , Alex Bereza , "Folker Schwesinger" , , , , , Subject: [PATCH V3 2/4] dmaengine: xilinx_dma: Move descriptors to done list based on completion bit Date: Wed, 8 Jul 2026 15:36:50 +0530 Message-ID: <20260708100652.603074-3-srinivas.neeli@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260708100652.603074-1-srinivas.neeli@amd.com> References: <20260708100652.603074-1-srinivas.neeli@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B074:EE_|DS0PR12MB9347:EE_ X-MS-Office365-Filtering-Correlation-Id: fdbbca9c-bc06-4e24-7a71-08dedcd8fca6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|7416014|23010399003|56012099006|6133799003|5023799004|22082099003|11063799006|18002099003; X-Microsoft-Antispam-Message-Info: CBofmeMnVE2FkWGYJUnUL07eHPwbqEZfDcTjYLgM0NrNeUgqSGQSAJIRxcOTrdWyxz+RBl62LbNjRFueQV6vjALVOT+t0y7UY+qewjeTZvkp3c8Cm99pHzDERAkE2uNMmJCRYUoQckjOiq88DxyRLck2btAIlW0vd4HMK8rV3xNSZub6AOQ0oYc7KlrH3670AabgbiLWbDT+ElYe0iSVyAeP7n9t5v5/7hmGPlBMb9XEgUFCyK69j9MKilovjXNBt8SLpjh8uEJ+i/ZZOUOzkFArJQIFsX3MfPxjDG15DySSeitAyeTZbFjNNAlB1rUI3IwPn3h0ekJEY6TS4U2c0+yVertjYf3rJEJa0bgCtEfJzx7qAhG/nygFuOVR58bMobS/yXFBFy387TEFeEvSCM/A5DKJSDe7XPIln99ml/V1U+4m1bHBHuth2+KGVXJBCE3NnvWg7X8p1FbmJopPGBFVnahpG4gNMquiRknXd+8Gwd9JmiM5wOZ4e//JZhqO+lrv4RGNPD/qFw8F+hfdS3gCw0gv18rWKJ1lfVEs+EvjVAZ+X7l06XFx+pKWP9tpuqM2wgeIZ3zYAKbSKhEDuSUxgiPCcs6OOFeZFROoIcaJ5jNbbNQzRBtz2EhUGv03XSouBlXR2/EuoQ8GeNdFNWX2h+7+1J6jmsS45Hru4lFVk7LAphTOBIuJlqxd63aqdeMVaOIe0zZbZkYm+8jz0w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(82310400026)(376014)(7416014)(23010399003)(56012099006)(6133799003)(5023799004)(22082099003)(11063799006)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: H3yiQ5socwUdQ9owVs4u1ZuMgMdrOCoCb9zNuRjhkXUFiE4vofWdj2SVv+4yI0H9WrkBBxoloOP4F+6nMG6G2xqLAiEpYP6YdKbB0rB6kcnVXT687Sd1qZFCxKN6rH+bnu7ec2IxFOscwsxEUz57TCJrJ+2Knb2poBPv8/XwvyIdk74HBELpUN0V4oob3NqBLkQXVlKuv8aT/SZWuvs/y0TRigygZz/Oxd10nzMNEkUlrVZsgp5VAB6JK2ACI7s1T7NiGGSjriGVpOQC6ZXbgD8VSgHHs1N2qNioRGPekAl/UcGCXXm8WjRgi5k2DXTE3M9AzwZGMdfPCdfTlpV73qKNUvHVvEqTFCsbw7b2aaZ3YqSvMd7/ubukoMzO7UOPacA36l3pmwKG1JhwBiuwOMmYxEHJRYhxMzgRZnsjeWliWMglnFUmn1uY873TVV5C X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2026 10:09:24.2603 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fdbbca9c-bc06-4e24-7a71-08dedcd8fca6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9347 In AXI MCDMA scatter-gather mode, xilinx_dma_complete_descriptor() walks the channel's active_list and unconditionally moves every entry to the done_list. The MCDMA IOC interrupt handler invokes this function on every interrupt-on-completion, but with interrupt coalescing (IRQThreshold > 1) an IOC interrupt may fire after only a subset of the queued descriptors have actually been processed by the hardware. As a result, descriptors whose completion bit is not yet set in the BD status were being reported as completed to client drivers. Add a check for the descriptor completion bit before moving entries from the active list to the done list, using the appropriate direction- specific status field (s2mm_status for DMA_DEV_TO_MEM, mm2s_status for DMA_MEM_TO_DEV). The MCDMA completion check is intentionally not guarded by chan->has_sg, unlike the AXIDMA branch above. AXI MCDMA only operates in scatter-gather mode (has_sg is always true), so the guard would always pass and is omitted. The completion bit is therefore checked unconditionally. Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support") Signed-off-by: Srinivas Neeli --- Changes in V3: - Added Fixes tag. - Expanded commit message to explain the interrupt coalescing scenario and why the has_sg guard is omitted for MCDMA. - Changed local variable from 'bool completed' to 'u32 status' for cleaner status field access. - Simplified completion check logic. Changes in V2: - No change. --- drivers/dma/xilinx/xilinx_dma.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index ff5b29a808e9..1b5b00f08c5f 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1784,6 +1784,17 @@ static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) struct xilinx_axidma_tx_segment, node); if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg) break; + } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { + struct xilinx_aximcdma_tx_segment *seg; + u32 status; + + seg = list_last_entry(&desc->segments, + struct xilinx_aximcdma_tx_segment, + node); + status = (chan->direction == DMA_DEV_TO_MEM) ? + seg->hw.s2mm_status : seg->hw.mm2s_status; + if (!(status & XILINX_DMA_BD_COMP_MASK)) + break; } if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA) -- 2.25.1