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Wed, 8 Jul 2026 20:00:33 -0700 From: Vishwaroop A To: Breno Leitao CC: Thierry Reding , Jon Hunter , Mark Brown , Laxman Dewangan , Sowjanya Komatineni , "Suresh Mangipudi" , Krishna Yarlagadda , , , Subject: Re: [PATCH v5 1/3] spi: tegra210-quad: Convert to hard IRQ with high-priority workqueue Date: Thu, 9 Jul 2026 03:00:33 +0000 Message-ID: <20260709030033.1753627-1-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: <20260708011257.1712961-1-va@nvidia.com> <20260708011257.1712961-2-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC4:EE_|DM3PR12MB9351:EE_ X-MS-Office365-Filtering-Correlation-Id: 6cca900c-c15a-49f2-1b2e-08dedd664b3a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|82310400026|36860700016|376014|18002099003|22082099003|4143699003|5023799004|11063799006|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tP+1yInDwtggrCj0aiEm2++IQwjppaL7Mabm5yGCciZMiVIk1/tP0X9bBKQuNzdjkCX7V3N7T0yAdZsMWbUR1iWSp0ZtMamTHnFED/lN72wIH6zhoB7ybMCtjJEtE1xgOdfYsO8hE1bjN5DvOb2rAsHarC9Zx72hLIyxXqObHfjl5Jw0/UnQ/Z/9PShZWkDgEF0pbL+fW/qjrTgc1bdFWcMxMhG2AjaGqEX+szC9wJVVkFONU6jUTHEPBbW7h56McClrxn0mFOMWA/5mvZzgOpP1QTLW9MOEMRdP2glP32OSd6Uu4YhhGSySB55+RE+SGr7MGGM9+SDHSIY2HJjGGBWGvEPUKiDixWlfqdBiO7XP0Q5m/qh6KSySFqn/COy3wJ/oSZSOaPE1cQhe/DAkxpkR+b7wnMsA2s/5LFg/rRIdkDOB8Zapoo/2YcBcuoPy X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2026 03:00:54.9189 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6cca900c-c15a-49f2-1b2e-08dedd664b3a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9351 On Wed, Jul 08, 2026 at 05:15:25AM -0700, Breno Leitao wrote: > I am still quite confused what tqspi->lock protects. In the code above, > you get the lock, then you dereference tqspi->curr_xfer, and then it > releases the lock, and use t later without any lock. Just the pointer read against the writers - tegra_qspi_setup_transfer_one() which publishes curr_xfer, and the completion paths which clear it. After the snapshot, t refers to the transfer that was current at that moment; later writes to tqspi->curr_xfer don't change t. The spi_transfer object itself is kept alive by the SPI core, not by this lock: tegra_qspi_{combined,non_combined}_seq_xfer() is parked in wait_for_completion_timeout(&tqspi->xfer_completion) for this xfer, so spi_finalize_current_message() cannot run and the message (and its spi_transfers) cannot be handed back to the caller until we - or the timeout path - signal xfer_completion. > if tqspi->lock() is protecting curr_xfer, shouldn't you hold it for > longer? Can't - wait_for_completion_interruptible_timeout() below sleeps, so holding spin_lock_irqsave() across it would trip scheduling-while-atomic and stall IRQs for the duration. handle_cpu_based_xfer() gets a single lock scope because it never sleeps; the DMA path has to split. Since v5, tegra_qspi_handle_timeout() also does cancel_work_sync(&tqspi->irq_work) before invoking handle_dma_based_xfer() itself (Mark's v4 concern), so the work handler and the timeout handler can't both be inside this function on the same transfer. Thanks, Vishwaroop