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Fri, 10 Jul 2026 11:12:04 -0700 (PDT) X-Received: by 2002:a17:90b:4ed0:b0:37f:bfd6:8b40 with SMTP id 98e67ed59e1d1-38dc74c25d3mr94846a91.5.1783707123891; Fri, 10 Jul 2026 11:12:03 -0700 (PDT) Received: from localhost ([50.35.46.84]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3117d847e17sm41239927eec.18.2026.07.10.11.12.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2026 11:12:03 -0700 (PDT) Date: Fri, 10 Jul 2026 11:11:59 -0700 From: Jonathan Cameron To: Andre Przywara Cc: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu , Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 01/16] arm_mpam: let low level MSC read accessors return an error Message-ID: <20260710111159.00001367@oss.qualcomm.com> In-Reply-To: <20260710144520.917375-2-andre.przywara@arm.com> References: <20260710144520.917375-1-andre.przywara@arm.com> <20260710144520.917375-2-andre.przywara@arm.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=LbIMLDfi c=1 sm=1 tr=0 ts=6a5135f5 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=qC1CW/w66vtJz1P9yTJxNA==:17 a=kj9zAlcOel0A:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=7CQSdrXTAAAA:8 a=q567kdKukifiGPTRiikA:9 a=CjuIK1q_8ugA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzEwMDE4MiBTYWx0ZWRfX2Z57lP7OVjrv 3dfuYrX9vWvk2QvSZVigP9eeRy+AVTj9sv3NkfnZafqKqi83ApMwKPWvp2rXWKdxMJDcGnHV/zV 09V240Aepy5/faRoLq6tSbCRKTyLL7NRwp4qNViam6jVaZ3aMWvljwIY+v9a7H6eLQsUaTTaLGM UMHVuqtpNc20MVvHdPLnlnjAzccdB3FdjDv4AIPF397mz4JiLrXlvz5DimRzmODO/7E9IifC06A 5WSN8UKfatQq6nsddegq6CF4nzwij+pPrZ+tiY8oiq4DRZLd03n9LoH1WVwU4ksEcvYCVl6XO/Y Aw23E5EHFxW+zd8LEmDKYw/Tjcj9PeM336YSj2kP/CMLmOLkrASeRxzO+rpbgE/CYyBI0YDFZz1 QcK+pkQ188/d50vOvDzb1YIHoAxm0+s3N72Msjoww2m8z12jnCE5n1BLXBHP9JDQ6YsChFaaztp ousNvf/7AilmHwiCoBA== X-Proofpoint-ORIG-GUID: YUX84urLWY4F-UrNUc7zZM44ByirOwxw X-Proofpoint-Spam-Info: AW1haW4tMjYwNzEwMDE4MiBTYWx0ZWRfX2HEqcxRhORH/ jWEj8uRiLAyt7eThsJEBRnu48d7u9cvP4tfT/G7MyflPusEIdCSe9B59/PX+TJNcAmrLBdscGwB YNirucyRue3nGXRlZVlisuBWD7mCwz4= X-Proofpoint-GUID: YUX84urLWY4F-UrNUc7zZM44ByirOwxw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-10_05,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1011 impostorscore=0 priorityscore=1501 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607100182 On Fri, 10 Jul 2026 16:45:05 +0200 Andre Przywara wrote: > The upcoming MPAM-Fb support does not use MMIO primitives to access an > MSC, but employs a shared-memory/doorbell based firmware protocol. > Its complexity means that is must be able to handle errors, whereas we > always assume an MSC access succeeds today. > > Change the __mpam_read_reg() low level accessor function to return the > requested data through a pointer, and return an error code instead. > At the moment this is always 0, but this will change with alternative > MSC access methods. > Change all users of those MSC read wrappers to comply with the new > prototype, though at the moment without propagating any errors. > > Signed-off-by: Andre Przywara Why do it in this order? It seems like it is a path for some code churn from patch to path. If you started at the outermost calls and worked in adding error handling at each layer, you wouldn't end up with the change here to add the parameter, then the same lines changed again to stash the new return value. Those lines would change just once. Maybe I'm wrong though and it ends up even messier. Or as you suggest, maybe just squash the patches, which will also remove the churn. Jonathan > @@ -226,10 +230,11 @@ static inline void _mpam_write_monsel_reg(struct mpam_msc *msc, u16 reg, u32 val > > static bool mpam_msc_check_aidr(struct mpam_msc *msc) > { > - u32 aidr = __mpam_read_reg(msc, MPAMF_AIDR); > - u32 major = FIELD_GET(MPAMF_AIDR_ARCH_MAJOR_REV, aidr); > - u32 minor = FIELD_GET(MPAMF_AIDR_ARCH_MINOR_REV, aidr); > + u32 aidr, major, minor; > > + __mpam_read_reg(msc, MPAMF_AIDR, &aidr); This will need updating to handle the error. If you were to instead do the patches in the opposite order. So add return value to the outer most calls that is always 0 then work your way in it should end up as a fair bit less code churn. That update is in a later patch. > + major = FIELD_GET(MPAMF_AIDR_ARCH_MAJOR_REV, aidr); > + minor = FIELD_GET(MPAMF_AIDR_ARCH_MINOR_REV, aidr); > /* > * v0.0 and >v2.x aren't supported, but anything else should be backward > * compatible to v0.1 or v1.0.