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Fri, 10 Jul 2026 12:14:38 -0700 (PDT) X-Received: by 2002:a05:6a21:6e96:b0:3bf:b523:2aed with SMTP id adf61e73a8af0-3c1100383fcmr321970637.8.1783710878257; Fri, 10 Jul 2026 12:14:38 -0700 (PDT) Received: from localhost ([50.35.46.84]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-311747f5975sm40574288eec.4.2026.07.10.12.14.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2026 12:14:37 -0700 (PDT) Date: Fri, 10 Jul 2026 12:14:33 -0700 From: Jonathan Cameron To: Andre Przywara Cc: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu , Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 13/16] arm_mpam: prepare mon_sel locking for MPAM-Fb Message-ID: <20260710121433.00001ad6@oss.qualcomm.com> In-Reply-To: <20260710144520.917375-14-andre.przywara@arm.com> References: <20260710144520.917375-1-andre.przywara@arm.com> <20260710144520.917375-14-andre.przywara@arm.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=JJYLdcKb c=1 sm=1 tr=0 ts=6a51449f cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=qC1CW/w66vtJz1P9yTJxNA==:17 a=kj9zAlcOel0A:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=7CQSdrXTAAAA:8 a=TWr3UOjz1xACnXJDHjEA:9 a=CjuIK1q_8ugA:10 a=IoOABgeZipijB_acs4fv:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-ORIG-GUID: qKq7Pw_qU3QV1FVdYu5nqc05zLtxajVD X-Proofpoint-Spam-Info: AW1haW4tMjYwNzEwMDE5MyBTYWx0ZWRfXwdnipyoJ+bnx S+lrHRWXntcr6S5Dza6+HB37iWOTRut/D4/VkPr7f2DF7hmjqjLmw3MceXh0MveaNM1ADxPv9Ki C2qEsZ74eJgIRUXKfEgrnd8eG9YIEic= X-Proofpoint-GUID: qKq7Pw_qU3QV1FVdYu5nqc05zLtxajVD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzEwMDE5MyBTYWx0ZWRfX0nRTQqOGkzuD U/jPvPnIFayu4vweYbKX6MKg6nKDt7EQabfx14lVYA9+V7udIcQBV3z1l9SIotsYQ4gUBuIfhVB 9ixK+BUSOw52kqs6G27SDpE296ZGBcKlGOctq3LsMQ0A9IR2nRt7Yqs7dBclXRsbnTC2j3OCKb4 cZmvLJl7TLcfar6QL95Weg9ftbjGSW2Pokyo/HpVsOm2OGEVbUzGzha3n8Vl9sn/0u6k5R3aLpK YQIVWVLuvkntQ+iVDqrqci6OCoDFgJ+4tvoKAUTTAuZN7hXZe/HemAuPcDOKrLekNG8nMvD9Hlu Bd5oobxZhtcQSDdhXXm21vPPZ/FeG5E2V9wyVUkoQPw7nYv9QYJEgjesLbFjYT8kt5swBn06unC 5kJ7h74SgubwgqhO18kgvF8dO2IfxAuLO1SBoMSmUXcgLpzEMWZBwx2gO2IUm1sGZBcPdqwVaUf /TvoQJN5YsEdIG2FADw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-10_05,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607100193 On Fri, 10 Jul 2026 16:45:17 +0200 Andre Przywara wrote: > The MSC MON_SEL register needs to be accessed from hardirq for the overflow > interrupt, and when taking an IPI to access these registers on platforms > where MSC are not accesible from every CPU. This makes an irqsave > spinlock the obvious lock to protect these registers. On systems with SCMI > mailboxes it must be able to sleep, meaning a mutex must be used. The > SCMI platforms can't support an overflow interrupt. > Clearly these two can't exist for one MSC at the same time. > > Change the mon_sel locking wrapper function to only use a spinlock when > the MSC is accessed directly via MMIO. In case of MPAM-Fb, we use a > mutex, but only if we are in a sleepable context. If that's not the > case, we return an error. This should not happen, as MPAM-Fb by design > does not require an MSC access to happen from a specific CPU, so there > is no need for any IPIs or preemption disabling to satisfy CPU > constraints. And since overflow interrupts are not supported at the moment > anyway, we also wouldn't meet the other case. > > Signed-off-by: Andre Przywara I've not been paying attention to this topic, so I might come back with some more feedback after I've had time to think about it a bit! So trivial stuff only for now. > > static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) > { > raw_spin_lock_init(&msc->_mon_sel_lock); > + mutex_init(&msc->mon_sel_mutex); I'm not that fussed, but maybe add a call to mutex_destroy(). Most likely it'll never help catch anything in this code though.. > } > > /* Bits for mpam features bitmaps */