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Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Corentin Labbe , linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 3/4] arm64: dts: rockchip: Add crypto node to rk356x-base Message-ID: <20260710153012.0a840512@enyo> In-Reply-To: <4011768.FjKLVJYuhi@diego> References: <20260708175837.1718437-1-dawidro@gmail.com> <20260708175837.1718437-4-dawidro@gmail.com> <4011768.FjKLVJYuhi@diego> X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Thu, 09 Jul 2026 09:07:23 +0200 Heiko St=C3=BCbner wrote: > Am Donnerstag, 9. Juli 2026, 01:56:10 Mitteleurop=C3=A4ische Sommerzeit > schrieb Sebastian Reichel: > > Hi, > >=20 > > On Wed, Jul 08, 2026 at 06:58:24PM +0100, Dawid Olesinski wrote: =20 > > > Add the device tree node for the V2 cryptographic hardware > > > accelerator on RK356x SoCs (RK3566, RK3568). > > >=20 > > > The IP block sits in the non-secure peripheral domain. Its three > > > clocks (core, aclk, hclk) and reset line are accessible directly > > > through the main non-secure CRU, so no firmware intermediary is > > > required. > > >=20 > > > The node is disabled by default; board files that wish to use > > > hardware crypto offload must enable it. =20 > >=20 > > Why is it disabled by default? It doesn't seem to be board specific > > at all to me (the same question applies to the RK3588 DT). =20 >=20 > You're definitly right about that ... there are no board specific > resources needed, so Dawid please drop the status from both nodes. >=20 >=20 > Heiko >=20 I'll drop the `status =3D "disabled";`=20 lines from both the RK356x and RK3588 device trees in v3. Thanks for the review! Dawid > > >=20 > > > Signed-off-by: Dawid Olesinski > > > --- > > > arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 12 ++++++++++++ > > > 1 file changed, 12 insertions(+) > > >=20 > > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi > > > b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index > > > a5832895bd39..9de7e7487ca1 100644 --- > > > a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ > > > b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1112,6 > > > +1112,18 @@ sdhci: mmc@fe310000 { status =3D "disabled"; > > > }; > > > =20 > > > + crypto: crypto@fe380000 { > > > + compatible =3D "rockchip,rk3568-crypto"; > > > + reg =3D <0x0 0xfe380000 0x0 0x2000>; > > > + interrupts =3D ; > > > + clocks =3D <&cru CLK_CRYPTO_NS_CORE>, <&cru > > > ACLK_CRYPTO_NS>, > > > + <&cru HCLK_CRYPTO_NS>; > > > + clock-names =3D "core", "aclk", "hclk"; > > > + resets =3D <&cru SRST_CRYPTO_NS_CORE>; > > > + reset-names =3D "core"; > > > + status =3D "disabled"; > > > + }; > > > + > > > /* > > > * Testing showed that the HWRNG found in RK3566 > > > produces unacceptably > > > * low quality of random data, so the HWRNG isn't > > > enabled for all RK356x =20 > > =20 >=20 >=20 >=20 >=20